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@@ -435,11 +435,6 @@ int hns_mac_get_sfp_prsnt(struct hns_mac_cb *mac_cb, int *sfp_prsnt)
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*/
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static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
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{
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- /* port 0-3 hilink4 base is serdes_vaddr + 0x00280000
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- * port 4-7 hilink3 base is serdes_vaddr + 0x00200000
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- */
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- u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
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- (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
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const u8 lane_id[] = {
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0, /* mac 0 -> lane 0 */
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1, /* mac 1 -> lane 1 */
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@@ -465,11 +460,30 @@ static int hns_mac_config_sds_loopback(struct hns_mac_cb *mac_cb, bool en)
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}
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if (mac_cb->serdes_ctrl) {
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- u32 origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
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+ u32 origin;
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+
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+ if (!AE_IS_VER1(mac_cb->dsaf_dev->dsaf_ver)) {
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+#define HILINK_ACCESS_SEL_CFG 0x40008
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+ /* hilink4 & hilink3 use the same xge training and
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+ * xge u adaptor. There is a hilink access sel cfg
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+ * register to select which one to be configed
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+ */
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+ if ((!HNS_DSAF_IS_DEBUG(mac_cb->dsaf_dev)) &&
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+ (mac_cb->mac_id <= 3))
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+ dsaf_write_syscon(mac_cb->serdes_ctrl,
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+ HILINK_ACCESS_SEL_CFG, 0);
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+ else
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+ dsaf_write_syscon(mac_cb->serdes_ctrl,
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+ HILINK_ACCESS_SEL_CFG, 3);
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+ }
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+
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+ origin = dsaf_read_syscon(mac_cb->serdes_ctrl, reg_offset);
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dsaf_set_field(origin, 1ull << 10, 10, en);
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dsaf_write_syscon(mac_cb->serdes_ctrl, reg_offset, origin);
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} else {
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+ u8 *base_addr = (u8 *)mac_cb->serdes_vaddr +
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+ (mac_cb->mac_id <= 3 ? 0x00280000 : 0x00200000);
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dsaf_set_reg_field(base_addr, reg_offset, 1ull << 10, 10, en);
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}
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