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@@ -1158,10 +1158,11 @@ static void kv_restore_regs_for_reset(struct amdgpu_device *adev,
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WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute);
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}
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-static void cik_gpu_pci_config_reset(struct amdgpu_device *adev)
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+static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
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{
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struct kv_reset_save_regs kv_save = { 0 };
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u32 i;
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+ int r = -EINVAL;
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dev_info(adev->dev, "GPU pci config reset\n");
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@@ -1177,14 +1178,18 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev)
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/* wait for asic to come out of reset */
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for (i = 0; i < adev->usec_timeout; i++) {
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- if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff)
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+ if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) {
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+ r = 0;
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break;
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+ }
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udelay(1);
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}
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/* does asic init need to be run first??? */
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if (adev->flags & AMD_IS_APU)
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kv_restore_regs_for_reset(adev, &kv_save);
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+
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+ return r;
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}
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static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
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@@ -1210,13 +1215,14 @@ static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hu
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*/
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static int cik_asic_reset(struct amdgpu_device *adev)
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{
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+ int r;
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cik_set_bios_scratch_engine_hung(adev, true);
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- cik_gpu_pci_config_reset(adev);
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+ r = cik_gpu_pci_config_reset(adev);
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cik_set_bios_scratch_engine_hung(adev, false);
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- return 0;
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+ return r;
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}
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static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
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