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@@ -130,6 +130,20 @@ static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
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static struct clk *clk[IMX5_CLK_END];
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static struct clk_onecell_data clk_data;
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+static struct clk ** const uart_clks[] __initconst = {
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+ &clk[IMX5_CLK_UART1_IPG_GATE],
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+ &clk[IMX5_CLK_UART1_PER_GATE],
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+ &clk[IMX5_CLK_UART2_IPG_GATE],
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+ &clk[IMX5_CLK_UART2_PER_GATE],
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+ &clk[IMX5_CLK_UART3_IPG_GATE],
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+ &clk[IMX5_CLK_UART3_PER_GATE],
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+ &clk[IMX5_CLK_UART4_IPG_GATE],
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+ &clk[IMX5_CLK_UART4_PER_GATE],
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+ &clk[IMX5_CLK_UART5_IPG_GATE],
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+ &clk[IMX5_CLK_UART5_PER_GATE],
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+ NULL
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+};
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+
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static void __init mx5_clocks_common_init(void __iomem *ccm_base)
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{
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clk[IMX5_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
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@@ -310,6 +324,8 @@ static void __init mx5_clocks_common_init(void __iomem *ccm_base)
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clk_prepare_enable(clk[IMX5_CLK_TMAX1]);
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clk_prepare_enable(clk[IMX5_CLK_TMAX2]); /* esdhc2, fec */
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clk_prepare_enable(clk[IMX5_CLK_TMAX3]); /* esdhc1, esdhc4 */
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+
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+ imx_register_uart_clocks(uart_clks);
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}
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static void __init mx50_clocks_init(struct device_node *np)
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