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+* STMicroelectronics Flexible Direct Memory Access Device Tree bindings
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+
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+The FDMA is a general-purpose direct memory access controller capable of
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+supporting 16 independent DMA channels. It accepts up to 32 DMA requests.
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+The FDMA is based on a Slim processor which requires a firmware.
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+
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+* FDMA Controller
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+
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+Required properties:
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+- compatible : Should be one of
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+ - st,stih407-fdma-mpe31-11, "st,slim-rproc";
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+ - st,stih407-fdma-mpe31-12, "st,slim-rproc";
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+ - st,stih407-fdma-mpe31-13, "st,slim-rproc";
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+- reg : Should contain an entry for each name in reg-names
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+- reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries
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+- interrupts : Should contain one interrupt shared by all channels
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+- dma-channels : Number of channels supported by the controller
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+- #dma-cells : Must be <3>. See DMA client section below
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+- clocks : Must contain an entry for each clock
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+See: Documentation/devicetree/bindings/clock/clock-bindings.txt
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+
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+
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+Example:
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+
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+ fdma0: dma-controller@8e20000 {
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+ compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc";
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+ reg = <0x8e20000 0x8000>,
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+ <0x8e30000 0x3000>,
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+ <0x8e37000 0x1000>,
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+ <0x8e38000 0x8000>;
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+ reg-names = "slimcore", "dmem", "peripherals", "imem";
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+ clocks = <&clk_s_c0_flexgen CLK_FDMA>,
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+ <&clk_s_c0_flexgen CLK_EXT2F_A9>,
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+ <&clk_s_c0_flexgen CLK_EXT2F_A9>,
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+ <&clk_s_c0_flexgen CLK_EXT2F_A9>;
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+ interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>;
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+ dma-channels = <16>;
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+ #dma-cells = <3>;
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+ };
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+
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+* DMA client
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+
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+Required properties:
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+- dmas: Comma separated list of dma channel requests
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+- dma-names: Names of the aforementioned requested channels
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+
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+Each dmas request consists of 4 cells:
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+1. A phandle pointing to the FDMA controller
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+2. The request line number
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+3. A 32bit mask specifying (see include/linux/platform_data/dma-st-fdma.h)
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+ -bit 2-0: Holdoff value, dreq will be masked for
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+ 0x0: 0-0.5us
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+ 0x1: 0.5-1us
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+ 0x2: 1-1.5us
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+ -bit 17: data swap
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+ 0x0: disabled
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+ 0x1: enabled
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+ -bit 21: Increment Address
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+ 0x0: no address increment between transfers
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+ 0x1: increment address between transfers
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+ -bit 22: 2 STBus Initiator Coprocessor interface
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+ 0x0: high priority port
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+ 0x1: low priority port
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+4. transfers type
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+ 0 free running
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+ 1 paced
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+
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+Example:
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+
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+ sti_uni_player2: sti-uni-player@2 {
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+ compatible = "st,sti-uni-player";
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+ status = "disabled";
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+ #sound-dai-cells = <0>;
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+ st,syscfg = <&syscfg_core>;
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+ clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
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+ assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_2>;
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+ assigned-clock-parents = <&clk_s_d0_quadfs 2>;
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+ assigned-clock-rates = <50000000>;
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+ reg = <0x8D82000 0x158>;
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+ interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
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+ dmas = <&fdma0 4 0 1>;
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+ dai-name = "Uni Player #1 (DAC)";
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+ dma-names = "tx";
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+ st,uniperiph-id = <2>;
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+ st,version = <5>;
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+ st,mode = "PCM";
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+ };
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