|
@@ -20,6 +20,7 @@
|
|
|
#include "omap_hwmod_33xx_43xx_common_data.h"
|
|
|
#include "prcm43xx.h"
|
|
|
#include "omap_hwmod_common_data.h"
|
|
|
+#include "hdq1w.h"
|
|
|
|
|
|
|
|
|
/* IP blocks */
|
|
@@ -516,6 +517,33 @@ static struct omap_hwmod am43xx_dss_rfbi_hwmod = {
|
|
|
.parent_hwmod = &am43xx_dss_core_hwmod,
|
|
|
};
|
|
|
|
|
|
+/* HDQ1W */
|
|
|
+static struct omap_hwmod_class_sysconfig am43xx_hdq1w_sysc = {
|
|
|
+ .rev_offs = 0x0000,
|
|
|
+ .sysc_offs = 0x0014,
|
|
|
+ .syss_offs = 0x0018,
|
|
|
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
|
|
|
+ .sysc_fields = &omap_hwmod_sysc_type1,
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod_class am43xx_hdq1w_hwmod_class = {
|
|
|
+ .name = "hdq1w",
|
|
|
+ .sysc = &am43xx_hdq1w_sysc,
|
|
|
+ .reset = &omap_hdq1w_reset,
|
|
|
+};
|
|
|
+
|
|
|
+static struct omap_hwmod am43xx_hdq1w_hwmod = {
|
|
|
+ .name = "hdq1w",
|
|
|
+ .class = &am43xx_hdq1w_hwmod_class,
|
|
|
+ .clkdm_name = "l4ls_clkdm",
|
|
|
+ .prcm = {
|
|
|
+ .omap4 = {
|
|
|
+ .clkctrl_offs = AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET,
|
|
|
+ .modulemode = MODULEMODE_SWCTRL,
|
|
|
+ },
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
/* Interfaces */
|
|
|
static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = {
|
|
|
.master = &am33xx_l3_main_hwmod,
|
|
@@ -790,6 +818,13 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__dss_rfbi = {
|
|
|
.user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
};
|
|
|
|
|
|
+static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = {
|
|
|
+ .master = &am33xx_l4_ls_hwmod,
|
|
|
+ .slave = &am43xx_hdq1w_hwmod,
|
|
|
+ .clk = "l4ls_gclk",
|
|
|
+ .user = OCP_USER_MPU | OCP_USER_SDMA,
|
|
|
+};
|
|
|
+
|
|
|
static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
|
|
|
&am33xx_l4_wkup__synctimer,
|
|
|
&am43xx_l4_ls__timer8,
|
|
@@ -889,6 +924,7 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = {
|
|
|
&am43xx_l4_ls__dss,
|
|
|
&am43xx_l4_ls__dss_dispc,
|
|
|
&am43xx_l4_ls__dss_rfbi,
|
|
|
+ &am43xx_l4_ls__hdq1w,
|
|
|
NULL,
|
|
|
};
|
|
|
|