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@@ -153,7 +153,7 @@ static int quad8_write_raw(struct iio_dev *indio_dev,
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ior_cfg = val | priv->preset_enable[chan->channel] << 1;
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/* Load I/O control configuration */
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- outb(0x40 | ior_cfg, base_offset);
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+ outb(0x40 | ior_cfg, base_offset + 1);
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return 0;
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case IIO_CHAN_INFO_SCALE:
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@@ -233,7 +233,7 @@ static ssize_t quad8_read_set_to_preset_on_index(struct iio_dev *indio_dev,
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const struct quad8_iio *const priv = iio_priv(indio_dev);
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return snprintf(buf, PAGE_SIZE, "%u\n",
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- priv->preset_enable[chan->channel]);
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+ !priv->preset_enable[chan->channel]);
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}
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static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev,
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@@ -241,7 +241,7 @@ static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev,
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size_t len)
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{
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struct quad8_iio *const priv = iio_priv(indio_dev);
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- const int base_offset = priv->base + 2 * chan->channel;
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+ const int base_offset = priv->base + 2 * chan->channel + 1;
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bool preset_enable;
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int ret;
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unsigned int ior_cfg;
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@@ -250,6 +250,9 @@ static ssize_t quad8_write_set_to_preset_on_index(struct iio_dev *indio_dev,
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if (ret)
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return ret;
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+ /* Preset enable is active low in Input/Output Control register */
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+ preset_enable = !preset_enable;
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+
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priv->preset_enable[chan->channel] = preset_enable;
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ior_cfg = priv->ab_enable[chan->channel] |
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@@ -362,7 +365,7 @@ static int quad8_set_synchronous_mode(struct iio_dev *indio_dev,
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priv->synchronous_mode[chan->channel] = synchronous_mode;
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/* Load Index Control configuration to Index Control Register */
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- outb(0x40 | idr_cfg, base_offset);
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+ outb(0x60 | idr_cfg, base_offset);
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return 0;
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}
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@@ -444,7 +447,7 @@ static int quad8_set_index_polarity(struct iio_dev *indio_dev,
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priv->index_polarity[chan->channel] = index_polarity;
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/* Load Index Control configuration to Index Control Register */
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- outb(0x40 | idr_cfg, base_offset);
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+ outb(0x60 | idr_cfg, base_offset);
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return 0;
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}
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