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+/*
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+ * Copyright © 2016 Intel Corporation
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice (including the next
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+ * paragraph) shall be included in all copies or substantial portions of the
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+ * Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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+ * IN THE SOFTWARE.
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+ *
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+ */
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+
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+#include "i915_drv.h"
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+#include "intel_ringbuffer.h"
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+#include "intel_lrc.h"
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+
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+static const struct engine_info {
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+ const char *name;
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+ unsigned exec_id;
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+ unsigned guc_id;
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+ u32 mmio_base;
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+ unsigned irq_shift;
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+ int (*init_legacy)(struct intel_engine_cs *engine);
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+ int (*init_execlists)(struct intel_engine_cs *engine);
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+} intel_engines[] = {
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+ [RCS] = {
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+ .name = "render ring",
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+ .exec_id = I915_EXEC_RENDER,
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+ .guc_id = GUC_RENDER_ENGINE,
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+ .mmio_base = RENDER_RING_BASE,
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+ .irq_shift = GEN8_RCS_IRQ_SHIFT,
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+ .init_execlists = logical_render_ring_init,
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+ .init_legacy = intel_init_render_ring_buffer,
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+ },
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+ [BCS] = {
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+ .name = "blitter ring",
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+ .exec_id = I915_EXEC_BLT,
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+ .guc_id = GUC_BLITTER_ENGINE,
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+ .mmio_base = BLT_RING_BASE,
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+ .irq_shift = GEN8_BCS_IRQ_SHIFT,
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+ .init_execlists = logical_xcs_ring_init,
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+ .init_legacy = intel_init_blt_ring_buffer,
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+ },
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+ [VCS] = {
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+ .name = "bsd ring",
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+ .exec_id = I915_EXEC_BSD,
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+ .guc_id = GUC_VIDEO_ENGINE,
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+ .mmio_base = GEN6_BSD_RING_BASE,
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+ .irq_shift = GEN8_VCS1_IRQ_SHIFT,
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+ .init_execlists = logical_xcs_ring_init,
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+ .init_legacy = intel_init_bsd_ring_buffer,
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+ },
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+ [VCS2] = {
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+ .name = "bsd2 ring",
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+ .exec_id = I915_EXEC_BSD,
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+ .guc_id = GUC_VIDEO_ENGINE2,
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+ .mmio_base = GEN8_BSD2_RING_BASE,
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+ .irq_shift = GEN8_VCS2_IRQ_SHIFT,
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+ .init_execlists = logical_xcs_ring_init,
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+ .init_legacy = intel_init_bsd2_ring_buffer,
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+ },
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+ [VECS] = {
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+ .name = "video enhancement ring",
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+ .exec_id = I915_EXEC_VEBOX,
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+ .guc_id = GUC_VIDEOENHANCE_ENGINE,
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+ .mmio_base = VEBOX_RING_BASE,
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+ .irq_shift = GEN8_VECS_IRQ_SHIFT,
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+ .init_execlists = logical_xcs_ring_init,
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+ .init_legacy = intel_init_vebox_ring_buffer,
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+ },
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+};
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+
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+static struct intel_engine_cs *
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+intel_engine_setup(struct drm_i915_private *dev_priv,
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+ enum intel_engine_id id)
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+{
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+ const struct engine_info *info = &intel_engines[id];
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+ struct intel_engine_cs *engine = &dev_priv->engine[id];
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+
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+ engine->id = id;
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+ engine->i915 = dev_priv;
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+ engine->name = info->name;
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+ engine->exec_id = info->exec_id;
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+ engine->hw_id = engine->guc_id = info->guc_id;
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+ engine->mmio_base = info->mmio_base;
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+ engine->irq_shift = info->irq_shift;
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+
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+ return engine;
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+}
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+
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+/**
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+ * intel_engines_init() - allocate, populate and init the Engine Command Streamers
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+ * @dev: DRM device.
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+ *
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+ * Return: non-zero if the initialization failed.
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+ */
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+int intel_engines_init(struct drm_device *dev)
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+{
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+ struct drm_i915_private *dev_priv = to_i915(dev);
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+ unsigned int mask = 0;
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+ int (*init)(struct intel_engine_cs *engine);
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+ unsigned int i;
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+ int ret;
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+
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+ WARN_ON(INTEL_INFO(dev_priv)->ring_mask &
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+ GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
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+
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+ for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
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+ if (!HAS_ENGINE(dev_priv, i))
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+ continue;
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+
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+ if (i915.enable_execlists)
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+ init = intel_engines[i].init_execlists;
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+ else
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+ init = intel_engines[i].init_legacy;
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+
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+ if (!init)
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+ continue;
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+
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+ ret = init(intel_engine_setup(dev_priv, i));
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+ if (ret)
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+ goto cleanup;
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+
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+ mask |= ENGINE_MASK(i);
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+ }
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+
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+ /*
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+ * Catch failures to update intel_engines table when the new engines
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+ * are added to the driver by a warning and disabling the forgotten
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+ * engines.
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+ */
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+ if (WARN_ON(mask != INTEL_INFO(dev_priv)->ring_mask)) {
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+ struct intel_device_info *info =
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+ (struct intel_device_info *)&dev_priv->info;
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+ info->ring_mask = mask;
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+ }
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+
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+ return 0;
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+
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+cleanup:
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+ for (i = 0; i < I915_NUM_ENGINES; i++) {
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+ if (i915.enable_execlists)
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+ intel_logical_ring_cleanup(&dev_priv->engine[i]);
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+ else
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+ intel_cleanup_engine(&dev_priv->engine[i]);
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+ }
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+
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+ return ret;
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+}
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+
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Tvrtko Ursulin