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@@ -1099,8 +1099,12 @@ struct i915_gpu_error {
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*/
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wait_queue_head_t reset_queue;
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- /* For gpu hang simulation. */
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- unsigned int stop_rings;
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+ /* Userspace knobs for gpu hang simulation;
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+ * combines both a ring mask, and extra flags
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+ */
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+ u32 stop_rings;
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+#define I915_STOP_RING_ALLOW_BAN (1 << 31)
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+#define I915_STOP_RING_ALLOW_WARN (1 << 30)
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/* For missed irq/seqno simulation. */
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unsigned int test_irq_rings;
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@@ -2146,6 +2150,18 @@ static inline u32 i915_reset_count(struct i915_gpu_error *error)
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return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
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}
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+static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
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+{
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+ return dev_priv->gpu_error.stop_rings == 0 ||
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+ dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
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+}
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+
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+static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
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+{
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+ return dev_priv->gpu_error.stop_rings == 0 ||
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+ dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
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+}
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+
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void i915_gem_reset(struct drm_device *dev);
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bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
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int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
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