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@@ -72,7 +72,6 @@
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#define BM_SPI_CS 0x20
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#define BM_SD_POWER 0x40
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#define BM_SOFT_RESET 0x80
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-#define BM_ONEBIT_MASK 0xFD
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/* SDMMC_BLKLEN bit fields */
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#define BLKL_CRCERR_ABORT 0x0800
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@@ -120,6 +119,8 @@
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#define STS2_DATARSP_BUSY 0x20
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#define STS2_DIS_FORCECLK 0x80
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+/* SDMMC_EXTCTRL bit fields */
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+#define EXT_EIGHTBIT 0x04
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/* MMC/SD DMA Controller Registers */
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#define SDDMA_GCR 0x100
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@@ -672,7 +673,7 @@ static void wmt_mci_request(struct mmc_host *mmc, struct mmc_request *req)
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static void wmt_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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{
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struct wmt_mci_priv *priv;
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- u32 reg_tmp;
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+ u32 busmode, extctrl;
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priv = mmc_priv(mmc);
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@@ -687,28 +688,26 @@ static void wmt_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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if (ios->clock != 0)
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clk_set_rate(priv->clk_sdmmc, ios->clock);
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+ busmode = readb(priv->sdmmc_base + SDMMC_BUSMODE);
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+ extctrl = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
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+
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+ busmode &= ~(BM_EIGHTBIT_MODE | BM_FOURBIT_MODE);
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+ extctrl &= ~EXT_EIGHTBIT;
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+
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switch (ios->bus_width) {
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case MMC_BUS_WIDTH_8:
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- reg_tmp = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
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- writeb(reg_tmp | 0x04, priv->sdmmc_base + SDMMC_EXTCTRL);
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+ busmode |= BM_EIGHTBIT_MODE;
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+ extctrl |= EXT_EIGHTBIT;
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break;
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case MMC_BUS_WIDTH_4:
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- reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
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- writeb(reg_tmp | BM_FOURBIT_MODE, priv->sdmmc_base +
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- SDMMC_BUSMODE);
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-
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- reg_tmp = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
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- writeb(reg_tmp & 0xFB, priv->sdmmc_base + SDMMC_EXTCTRL);
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+ busmode |= BM_FOURBIT_MODE;
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break;
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case MMC_BUS_WIDTH_1:
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- reg_tmp = readb(priv->sdmmc_base + SDMMC_BUSMODE);
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- writeb(reg_tmp & BM_ONEBIT_MASK, priv->sdmmc_base +
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- SDMMC_BUSMODE);
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-
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- reg_tmp = readb(priv->sdmmc_base + SDMMC_EXTCTRL);
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- writeb(reg_tmp & 0xFB, priv->sdmmc_base + SDMMC_EXTCTRL);
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break;
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}
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+
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+ writeb(busmode, priv->sdmmc_base + SDMMC_BUSMODE);
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+ writeb(extctrl, priv->sdmmc_base + SDMMC_EXTCTRL);
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}
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static int wmt_mci_get_ro(struct mmc_host *mmc)
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