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@@ -379,13 +379,33 @@ gen7_render_ring_flush(struct intel_engine_cs *ring,
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return 0;
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}
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+static int
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+gen8_emit_pipe_control(struct intel_engine_cs *ring,
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+ u32 flags, u32 scratch_addr)
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+{
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+ int ret;
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+
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+ ret = intel_ring_begin(ring, 6);
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+ if (ret)
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+ return ret;
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+
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+ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
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+ intel_ring_emit(ring, flags);
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+ intel_ring_emit(ring, scratch_addr);
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+ intel_ring_emit(ring, 0);
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+ intel_ring_emit(ring, 0);
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+ intel_ring_emit(ring, 0);
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+ intel_ring_advance(ring);
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+
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+ return 0;
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+}
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+
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static int
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gen8_render_ring_flush(struct intel_engine_cs *ring,
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u32 invalidate_domains, u32 flush_domains)
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{
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u32 flags = 0;
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u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES;
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- int ret;
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flags |= PIPE_CONTROL_CS_STALL;
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@@ -404,20 +424,7 @@ gen8_render_ring_flush(struct intel_engine_cs *ring,
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flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
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}
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- ret = intel_ring_begin(ring, 6);
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- if (ret)
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- return ret;
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-
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- intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
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- intel_ring_emit(ring, flags);
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- intel_ring_emit(ring, scratch_addr);
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- intel_ring_emit(ring, 0);
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- intel_ring_emit(ring, 0);
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- intel_ring_emit(ring, 0);
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- intel_ring_advance(ring);
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-
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- return 0;
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-
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+ return gen8_emit_pipe_control(ring, flags, scratch_addr);
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}
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static void ring_write_tail(struct intel_engine_cs *ring,
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