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@@ -132,6 +132,7 @@ struct aspeed_i2c_bus {
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/* Synchronizes I/O mem access to base. */
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spinlock_t lock;
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struct completion cmd_complete;
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+ u32 (*get_clk_reg_val)(u32 divisor);
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unsigned long parent_clk_frequency;
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u32 bus_frequency;
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/* Transaction state. */
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@@ -674,7 +675,7 @@ static const struct i2c_algorithm aspeed_i2c_algo = {
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#endif /* CONFIG_I2C_SLAVE */
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};
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-static u32 aspeed_i2c_get_clk_reg_val(u32 divisor)
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+static u32 aspeed_i2c_get_clk_reg_val(u32 clk_high_low_max, u32 divisor)
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{
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u32 base_clk, clk_high, clk_low, tmp;
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@@ -694,16 +695,22 @@ static u32 aspeed_i2c_get_clk_reg_val(u32 divisor)
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* Thus,
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* SCL_freq = APB_freq /
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* ((1 << base_clk) * (clk_high + 1 + clk_low + 1))
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- * The documentation recommends clk_high >= 8 and clk_low >= 7 when
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- * possible; this last constraint gives us the following solution:
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+ * The documentation recommends clk_high >= clk_high_max / 2 and
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+ * clk_low >= clk_low_max / 2 - 1 when possible; this last constraint
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+ * gives us the following solution:
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*/
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- base_clk = divisor > 33 ? ilog2((divisor - 1) / 32) + 1 : 0;
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- tmp = divisor / (1 << base_clk);
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- clk_high = tmp / 2 + tmp % 2;
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- clk_low = tmp - clk_high;
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+ base_clk = divisor > clk_high_low_max ?
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+ ilog2((divisor - 1) / clk_high_low_max) + 1 : 0;
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+ tmp = (divisor + (1 << base_clk) - 1) >> base_clk;
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+ clk_low = tmp / 2;
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+ clk_high = tmp - clk_low;
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+
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+ if (clk_high)
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+ clk_high--;
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+
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+ if (clk_low)
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+ clk_low--;
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- clk_high -= 1;
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- clk_low -= 1;
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return ((clk_high << ASPEED_I2CD_TIME_SCL_HIGH_SHIFT)
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& ASPEED_I2CD_TIME_SCL_HIGH_MASK)
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@@ -712,13 +719,31 @@ static u32 aspeed_i2c_get_clk_reg_val(u32 divisor)
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| (base_clk & ASPEED_I2CD_TIME_BASE_DIVISOR_MASK);
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}
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+static u32 aspeed_i2c_24xx_get_clk_reg_val(u32 divisor)
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+{
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+ /*
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+ * clk_high and clk_low are each 3 bits wide, so each can hold a max
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+ * value of 8 giving a clk_high_low_max of 16.
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+ */
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+ return aspeed_i2c_get_clk_reg_val(16, divisor);
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+}
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+
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+static u32 aspeed_i2c_25xx_get_clk_reg_val(u32 divisor)
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+{
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+ /*
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+ * clk_high and clk_low are each 4 bits wide, so each can hold a max
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+ * value of 16 giving a clk_high_low_max of 32.
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+ */
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+ return aspeed_i2c_get_clk_reg_val(32, divisor);
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+}
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+
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/* precondition: bus.lock has been acquired. */
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static int aspeed_i2c_init_clk(struct aspeed_i2c_bus *bus)
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{
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u32 divisor, clk_reg_val;
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- divisor = bus->parent_clk_frequency / bus->bus_frequency;
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- clk_reg_val = aspeed_i2c_get_clk_reg_val(divisor);
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+ divisor = DIV_ROUND_UP(bus->parent_clk_frequency, bus->bus_frequency);
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+ clk_reg_val = bus->get_clk_reg_val(divisor);
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writel(clk_reg_val, bus->base + ASPEED_I2C_AC_TIMING_REG1);
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writel(ASPEED_NO_TIMEOUT_CTRL, bus->base + ASPEED_I2C_AC_TIMING_REG2);
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@@ -777,8 +802,22 @@ static int aspeed_i2c_reset(struct aspeed_i2c_bus *bus)
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return ret;
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}
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+static const struct of_device_id aspeed_i2c_bus_of_table[] = {
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+ {
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+ .compatible = "aspeed,ast2400-i2c-bus",
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+ .data = aspeed_i2c_24xx_get_clk_reg_val,
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+ },
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+ {
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+ .compatible = "aspeed,ast2500-i2c-bus",
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+ .data = aspeed_i2c_25xx_get_clk_reg_val,
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+ },
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+ { },
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+};
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+MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
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+
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static int aspeed_i2c_probe_bus(struct platform_device *pdev)
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{
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+ const struct of_device_id *match;
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struct aspeed_i2c_bus *bus;
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struct clk *parent_clk;
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struct resource *res;
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@@ -808,6 +847,12 @@ static int aspeed_i2c_probe_bus(struct platform_device *pdev)
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bus->bus_frequency = 100000;
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}
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+ match = of_match_node(aspeed_i2c_bus_of_table, pdev->dev.of_node);
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+ if (!match)
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+ bus->get_clk_reg_val = aspeed_i2c_24xx_get_clk_reg_val;
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+ else
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+ bus->get_clk_reg_val = match->data;
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+
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/* Initialize the I2C adapter */
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spin_lock_init(&bus->lock);
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init_completion(&bus->cmd_complete);
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@@ -869,13 +914,6 @@ static int aspeed_i2c_remove_bus(struct platform_device *pdev)
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return 0;
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}
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-static const struct of_device_id aspeed_i2c_bus_of_table[] = {
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- { .compatible = "aspeed,ast2400-i2c-bus", },
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- { .compatible = "aspeed,ast2500-i2c-bus", },
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- { },
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-};
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-MODULE_DEVICE_TABLE(of, aspeed_i2c_bus_of_table);
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-
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static struct platform_driver aspeed_i2c_bus_driver = {
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.probe = aspeed_i2c_probe_bus,
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.remove = aspeed_i2c_remove_bus,
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