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@@ -2747,6 +2747,9 @@ static void dce110_program_front_end_for_pipe(
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struct dc_plane_state *plane_state = pipe_ctx->plane_state;
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struct xfm_grph_csc_adjustment adjust;
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struct out_csc_color_matrix tbl_entry;
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+#if defined(CONFIG_DRM_AMD_DC_FBC)
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+ unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
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+#endif
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unsigned int i;
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DC_LOGGER_INIT();
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memset(&tbl_entry, 0, sizeof(tbl_entry));
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@@ -2788,7 +2791,9 @@ static void dce110_program_front_end_for_pipe(
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program_scaler(dc, pipe_ctx);
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#if defined(CONFIG_DRM_AMD_DC_FBC)
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- if (dc->fbc_compressor && old_pipe->stream) {
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+ /* fbc not applicable on Underlay pipe */
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+ if (dc->fbc_compressor && old_pipe->stream &&
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+ pipe_ctx->pipe_idx != underlay_idx) {
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if (plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
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dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
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else
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