drm/nouveau/disp: namespace + nvidia gpu names (no binary change)

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/include/nvkm/core/os.h

@@ -245,5 +245,8 @@
 #define nouveau_fuse nvkm_fuse
 #define nouveau_mc nvkm_mc
 #define nouveau_mmu nvkm_mmu
+#define nouveau_dmaeng nvkm_dmaeng
+#define nouveau_dmaobj nvkm_dmaobj
+#define nouveau_disp nvkm_disp
 
 #endif

drivers/gpu/drm/nouveau/include/nvkm/engine/disp.h

@@ -1,13 +1,10 @@
-#ifndef __NOUVEAU_DISP_H__
-#define __NOUVEAU_DISP_H__
-
-#include <core/object.h>
+#ifndef __NVKM_DISP_H__
+#define __NVKM_DISP_H__
 #include <core/engine.h>
-#include <core/device.h>
 #include <core/event.h>
 
-struct nouveau_disp {
-	struct nouveau_engine base;
+struct nvkm_disp {
+	struct nvkm_engine base;
 
 	struct list_head outp;
 
@@ -15,22 +12,21 @@ struct nouveau_disp {
 	struct nvkm_event vblank;
 };
 
-static inline struct nouveau_disp *
-nouveau_disp(void *obj)
+static inline struct nvkm_disp *
+nvkm_disp(void *obj)
 {
-	return (void *)nouveau_engine(obj, NVDEV_ENGINE_DISP);
+	return (void *)nvkm_engine(obj, NVDEV_ENGINE_DISP);
 }
 
-extern struct nouveau_oclass *nv04_disp_oclass;
-extern struct nouveau_oclass *nv50_disp_oclass;
-extern struct nouveau_oclass *nv84_disp_oclass;
-extern struct nouveau_oclass *nva0_disp_oclass;
-extern struct nouveau_oclass *nv94_disp_oclass;
-extern struct nouveau_oclass *nva3_disp_oclass;
-extern struct nouveau_oclass *nvd0_disp_oclass;
-extern struct nouveau_oclass *nve0_disp_oclass;
-extern struct nouveau_oclass *nvf0_disp_oclass;
-extern struct nouveau_oclass *gm107_disp_oclass;
-extern struct nouveau_oclass *gm204_disp_oclass;
-
+extern struct nvkm_oclass *nv04_disp_oclass;
+extern struct nvkm_oclass *nv50_disp_oclass;
+extern struct nvkm_oclass *g84_disp_oclass;
+extern struct nvkm_oclass *gt200_disp_oclass;
+extern struct nvkm_oclass *g94_disp_oclass;
+extern struct nvkm_oclass *gt215_disp_oclass;
+extern struct nvkm_oclass *gf110_disp_oclass;
+extern struct nvkm_oclass *gk104_disp_oclass;
+extern struct nvkm_oclass *gk110_disp_oclass;
+extern struct nvkm_oclass *gm107_disp_oclass;
+extern struct nvkm_oclass *gm204_disp_oclass;
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c

@@ -113,7 +113,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
 		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv84_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
 	case 0x86:
@@ -142,7 +142,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
 		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv84_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
 	case 0x92:
@@ -171,7 +171,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
 		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv84_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
 	case 0x94:
@@ -200,7 +200,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
 		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
 	case 0x96:
@@ -229,7 +229,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
 		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
 	case 0x98:
@@ -258,7 +258,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
 	case 0xa0:
@@ -287,7 +287,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
 		device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
 		device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva0_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt200_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
 	case 0xaa:
@@ -316,7 +316,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
 	case 0xac:
@@ -345,7 +345,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
 		break;
 	case 0xa3:
@@ -376,7 +376,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;
 		break;
 	case 0xa5:
@@ -406,7 +406,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;
 		break;
 	case 0xa8:
@@ -436,7 +436,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;
 		break;
 	case 0xaf:
@@ -466,7 +466,7 @@ nv50_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;
 		break;
 	default:

drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c

@@ -89,7 +89,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gf100_ce1_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
 		break;
 	case 0xc4:
@@ -122,7 +122,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gf100_ce1_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
 		break;
 	case 0xc3:
@@ -154,7 +154,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
 		break;
 	case 0xce:
@@ -187,7 +187,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gf100_ce1_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
 		break;
 	case 0xcf:
@@ -219,7 +219,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
 		break;
 	case 0xc1:
@@ -251,7 +251,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
 		break;
 	case 0xc8:
@@ -284,7 +284,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gf100_ce1_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
 		break;
 	case 0xd9:
@@ -316,7 +316,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvd0_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gf110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
 		break;
 	case 0xd7:
@@ -346,7 +346,7 @@ nvc0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
 		device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gf100_ce0_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvd0_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gf110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
 		break;
 	default:

drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c

@@ -84,7 +84,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
@@ -118,7 +118,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
@@ -152,7 +152,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  nve4_gr_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nve0_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gk104_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
@@ -208,7 +208,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  nvf0_gr_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
@@ -242,7 +242,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nve0_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  gk110b_gr_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
@@ -276,7 +276,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_gr_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
@@ -309,7 +309,7 @@ nve0_identify(struct nouveau_device *device)
 		device->oclass[NVDEV_ENGINE_FIFO   ] =  nv108_fifo_oclass;
 		device->oclass[NVDEV_ENGINE_SW     ] =  nvc0_sw_oclass;
 		device->oclass[NVDEV_ENGINE_GR     ] =  nv108_gr_oclass;
-		device->oclass[NVDEV_ENGINE_DISP   ] =  nvf0_disp_oclass;
+		device->oclass[NVDEV_ENGINE_DISP   ] =  gk110_disp_oclass;
 		device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
 		device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
 		device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;

drivers/gpu/drm/nouveau/nvkm/engine/disp/Kbuild

@@ -4,26 +4,26 @@ nvkm-y += nvkm/engine/disp/outp.o
 nvkm-y += nvkm/engine/disp/outpdp.o
 nvkm-y += nvkm/engine/disp/nv04.o
 nvkm-y += nvkm/engine/disp/nv50.o
-nvkm-y += nvkm/engine/disp/nv84.o
-nvkm-y += nvkm/engine/disp/nv94.o
-nvkm-y += nvkm/engine/disp/nva0.o
-nvkm-y += nvkm/engine/disp/nva3.o
-nvkm-y += nvkm/engine/disp/nvd0.o
-nvkm-y += nvkm/engine/disp/nve0.o
-nvkm-y += nvkm/engine/disp/nvf0.o
+nvkm-y += nvkm/engine/disp/g84.o
+nvkm-y += nvkm/engine/disp/g94.o
+nvkm-y += nvkm/engine/disp/gt200.o
+nvkm-y += nvkm/engine/disp/gt215.o
+nvkm-y += nvkm/engine/disp/gf110.o
+nvkm-y += nvkm/engine/disp/gk104.o
+nvkm-y += nvkm/engine/disp/gk110.o
 nvkm-y += nvkm/engine/disp/gm107.o
 nvkm-y += nvkm/engine/disp/gm204.o
 nvkm-y += nvkm/engine/disp/dacnv50.o
 nvkm-y += nvkm/engine/disp/dport.o
-nvkm-y += nvkm/engine/disp/hdanva3.o
-nvkm-y += nvkm/engine/disp/hdanvd0.o
-nvkm-y += nvkm/engine/disp/hdminv84.o
-nvkm-y += nvkm/engine/disp/hdminva3.o
-nvkm-y += nvkm/engine/disp/hdminvd0.o
-nvkm-y += nvkm/engine/disp/hdminve0.o
+nvkm-y += nvkm/engine/disp/hdagt215.o
+nvkm-y += nvkm/engine/disp/hdagf110.o
+nvkm-y += nvkm/engine/disp/hdmig84.o
+nvkm-y += nvkm/engine/disp/hdmigt215.o
+nvkm-y += nvkm/engine/disp/hdmigf110.o
+nvkm-y += nvkm/engine/disp/hdmigk104.o
 nvkm-y += nvkm/engine/disp/piornv50.o
 nvkm-y += nvkm/engine/disp/sornv50.o
-nvkm-y += nvkm/engine/disp/sornv94.o
-nvkm-y += nvkm/engine/disp/sornvd0.o
+nvkm-y += nvkm/engine/disp/sorg94.o
+nvkm-y += nvkm/engine/disp/sorgf110.o
 nvkm-y += nvkm/engine/disp/sorgm204.o
 nvkm-y += nvkm/engine/disp/vga.o

drivers/gpu/drm/nouveau/nvkm/engine/disp/base.c

@@ -21,21 +21,23 @@
  *
  * Authors: Ben Skeggs
  */
+#include "priv.h"
+#include "conn.h"
+#include "outp.h"
+
+#include <core/notify.h>
+#include <subdev/bios.h>
+#include <subdev/bios/dcb.h>
 
-#include <core/os.h>
-#include <nvif/unpack.h>
 #include <nvif/class.h>
 #include <nvif/event.h>
-
-#include "priv.h"
-#include "outp.h"
-#include "conn.h"
+#include <nvif/unpack.h>
 
 int
-nouveau_disp_vblank_ctor(struct nouveau_object *object, void *data, u32 size,
-			 struct nvkm_notify *notify)
+nvkm_disp_vblank_ctor(struct nvkm_object *object, void *data, u32 size,
+		      struct nvkm_notify *notify)
 {
-	struct nouveau_disp *disp =
+	struct nvkm_disp *disp =
 		container_of(notify->event, typeof(*disp), vblank);
 	union {
 		struct nvif_notify_head_req_v0 v0;
@@ -55,17 +57,17 @@ nouveau_disp_vblank_ctor(struct nouveau_object *object, void *data, u32 size,
 }
 
 void
-nouveau_disp_vblank(struct nouveau_disp *disp, int head)
+nvkm_disp_vblank(struct nvkm_disp *disp, int head)
 {
 	struct nvif_notify_head_rep_v0 rep = {};
 	nvkm_event_send(&disp->vblank, 1, head, &rep, sizeof(rep));
 }
 
 static int
-nouveau_disp_hpd_ctor(struct nouveau_object *object, void *data, u32 size,
-		      struct nvkm_notify *notify)
+nvkm_disp_hpd_ctor(struct nvkm_object *object, void *data, u32 size,
+		   struct nvkm_notify *notify)
 {
-	struct nouveau_disp *disp =
+	struct nvkm_disp *disp =
 		container_of(notify->event, typeof(*disp), hpd);
 	union {
 		struct nvif_notify_conn_req_v0 v0;
@@ -91,15 +93,14 @@ nouveau_disp_hpd_ctor(struct nouveau_object *object, void *data, u32 size,
 }
 
 static const struct nvkm_event_func
-nouveau_disp_hpd_func = {
-	.ctor = nouveau_disp_hpd_ctor
+nvkm_disp_hpd_func = {
+	.ctor = nvkm_disp_hpd_ctor
 };
 
 int
-nouveau_disp_ntfy(struct nouveau_object *object, u32 type,
-		  struct nvkm_event **event)
+nvkm_disp_ntfy(struct nvkm_object *object, u32 type, struct nvkm_event **event)
 {
-	struct nouveau_disp *disp = (void *)object->engine;
+	struct nvkm_disp *disp = (void *)object->engine;
 	switch (type) {
 	case NV04_DISP_NTFY_VBLANK:
 		*event = &disp->vblank;
@@ -114,9 +115,9 @@ nouveau_disp_ntfy(struct nouveau_object *object, u32 type,
 }
 
 int
-_nouveau_disp_fini(struct nouveau_object *object, bool suspend)
+_nvkm_disp_fini(struct nvkm_object *object, bool suspend)
 {
-	struct nouveau_disp *disp = (void *)object;
+	struct nvkm_disp *disp = (void *)object;
 	struct nvkm_output *outp;
 	int ret;
 
@@ -126,7 +127,7 @@ _nouveau_disp_fini(struct nouveau_object *object, bool suspend)
 			goto fail_outp;
 	}
 
-	return nouveau_engine_fini(&disp->base, suspend);
+	return nvkm_engine_fini(&disp->base, suspend);
 
 fail_outp:
 	list_for_each_entry_continue_reverse(outp, &disp->outp, head) {
@@ -137,13 +138,13 @@ fail_outp:
 }
 
 int
-_nouveau_disp_init(struct nouveau_object *object)
+_nvkm_disp_init(struct nvkm_object *object)
 {
-	struct nouveau_disp *disp = (void *)object;
+	struct nvkm_disp *disp = (void *)object;
 	struct nvkm_output *outp;
 	int ret;
 
-	ret = nouveau_engine_init(&disp->base);
+	ret = nvkm_engine_init(&disp->base);
 	if (ret)
 		return ret;
 
@@ -164,9 +165,9 @@ fail_outp:
 }
 
 void
-_nouveau_disp_dtor(struct nouveau_object *object)
+_nvkm_disp_dtor(struct nvkm_object *object)
 {
-	struct nouveau_disp *disp = (void *)object;
+	struct nvkm_disp *disp = (void *)object;
 	struct nvkm_output *outp, *outt;
 
 	nvkm_event_fini(&disp->vblank);
@@ -174,32 +175,30 @@ _nouveau_disp_dtor(struct nouveau_object *object)
 
 	if (disp->outp.next) {
 		list_for_each_entry_safe(outp, outt, &disp->outp, head) {
-			nouveau_object_ref(NULL, (struct nouveau_object **)&outp);
+			nvkm_object_ref(NULL, (struct nvkm_object **)&outp);
 		}
 	}
 
-	nouveau_engine_destroy(&disp->base);
+	nvkm_engine_destroy(&disp->base);
 }
 
 int
-nouveau_disp_create_(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, int heads,
-		     const char *intname, const char *extname,
-		     int length, void **pobject)
+nvkm_disp_create_(struct nvkm_object *parent, struct nvkm_object *engine,
+		  struct nvkm_oclass *oclass, int heads, const char *intname,
+		  const char *extname, int length, void **pobject)
 {
-	struct nouveau_disp_impl *impl = (void *)oclass;
-	struct nouveau_bios *bios = nouveau_bios(parent);
-	struct nouveau_disp *disp;
-	struct nouveau_oclass **sclass;
-	struct nouveau_object *object;
+	struct nvkm_disp_impl *impl = (void *)oclass;
+	struct nvkm_bios *bios = nvkm_bios(parent);
+	struct nvkm_disp *disp;
+	struct nvkm_oclass **sclass;
+	struct nvkm_object *object;
 	struct dcb_output dcbE;
 	u8  hpd = 0, ver, hdr;
 	u32 data;
 	int ret, i;
 
-	ret = nouveau_engine_create_(parent, engine, oclass, true,
-				     intname, extname, length, pobject);
+	ret = nvkm_engine_create_(parent, engine, oclass, true, intname,
+				  extname, length, pobject);
 	disp = *pobject;
 	if (ret)
 		return ret;
@@ -225,11 +224,11 @@ nouveau_disp_create_(struct nouveau_object *parent,
 			sclass++;
 		}
 
-		nouveau_object_ctor(*pobject, NULL, oclass, &dcbE, i, &object);
+		nvkm_object_ctor(*pobject, NULL, oclass, &dcbE, i, &object);
 		hpd = max(hpd, (u8)(dcbE.connector + 1));
 	}
 
-	ret = nvkm_event_init(&nouveau_disp_hpd_func, 3, hpd, &disp->hpd);
+	ret = nvkm_event_init(&nvkm_disp_hpd_func, 3, hpd, &disp->hpd);
 	if (ret)
 		return ret;
 

drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.c

@@ -21,21 +21,20 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <core/os.h>
-#include <nvif/event.h>
+#include "conn.h"
+#include "outp.h"
+#include "priv.h"
 
 #include <subdev/gpio.h>
 
-#include "conn.h"
-#include "outp.h"
+#include <nvif/event.h>
 
 static int
 nvkm_connector_hpd(struct nvkm_notify *notify)
 {
 	struct nvkm_connector *conn = container_of(notify, typeof(*conn), hpd);
-	struct nouveau_disp *disp = nouveau_disp(conn);
-	struct nouveau_gpio *gpio = nouveau_gpio(conn);
+	struct nvkm_disp *disp = nvkm_disp(conn);
+	struct nvkm_gpio *gpio = nvkm_gpio(conn);
 	const struct nvkm_gpio_ntfy_rep *line = notify->data;
 	struct nvif_notify_conn_rep_v0 rep;
 	int index = conn->index;
@@ -53,41 +52,41 @@ nvkm_connector_hpd(struct nvkm_notify *notify)
 }
 
 int
-_nvkm_connector_fini(struct nouveau_object *object, bool suspend)
+_nvkm_connector_fini(struct nvkm_object *object, bool suspend)
 {
 	struct nvkm_connector *conn = (void *)object;
 	nvkm_notify_put(&conn->hpd);
-	return nouveau_object_fini(&conn->base, suspend);
+	return nvkm_object_fini(&conn->base, suspend);
 }
 
 int
-_nvkm_connector_init(struct nouveau_object *object)
+_nvkm_connector_init(struct nvkm_object *object)
 {
 	struct nvkm_connector *conn = (void *)object;
-	int ret = nouveau_object_init(&conn->base);
+	int ret = nvkm_object_init(&conn->base);
 	if (ret == 0)
 		nvkm_notify_get(&conn->hpd);
 	return ret;
 }
 
 void
-_nvkm_connector_dtor(struct nouveau_object *object)
+_nvkm_connector_dtor(struct nvkm_object *object)
 {
 	struct nvkm_connector *conn = (void *)object;
 	nvkm_notify_fini(&conn->hpd);
-	nouveau_object_destroy(&conn->base);
+	nvkm_object_destroy(&conn->base);
 }
 
 int
-nvkm_connector_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass,
+nvkm_connector_create_(struct nvkm_object *parent,
+		       struct nvkm_object *engine,
+		       struct nvkm_oclass *oclass,
 		       struct nvbios_connE *info, int index,
 		       int length, void **pobject)
 {
 	static const u8 hpd[] = { 0x07, 0x08, 0x51, 0x52, 0x5e, 0x5f, 0x60 };
-	struct nouveau_disp *disp = nouveau_disp(parent);
-	struct nouveau_gpio *gpio = nouveau_gpio(parent);
+	struct nvkm_disp *disp = nvkm_disp(parent);
+	struct nvkm_gpio *gpio = nvkm_gpio(parent);
 	struct nvkm_connector *conn;
 	struct nvkm_output *outp;
 	struct dcb_gpio_func func;
@@ -101,7 +100,7 @@ nvkm_connector_create_(struct nouveau_object *parent,
 		}
 	}
 
-	ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject);
+	ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject);
 	conn = *pobject;
 	if (ret)
 		return ret;
@@ -145,10 +144,10 @@ nvkm_connector_create_(struct nouveau_object *parent,
 }
 
 int
-_nvkm_connector_ctor(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, void *info, u32 index,
-		     struct nouveau_object **pobject)
+_nvkm_connector_ctor(struct nvkm_object *parent,
+		     struct nvkm_object *engine,
+		     struct nvkm_oclass *oclass, void *info, u32 index,
+		     struct nvkm_object **pobject)
 {
 	struct nvkm_connector *conn;
 	int ret;
@@ -161,11 +160,11 @@ _nvkm_connector_ctor(struct nouveau_object *parent,
 	return 0;
 }
 
-struct nouveau_oclass *
+struct nvkm_oclass *
 nvkm_connector_oclass = &(struct nvkm_connector_impl) {
 	.base = {
 		.handle = 0,
-		.ofuncs = &(struct nouveau_ofuncs) {
+		.ofuncs = &(struct nvkm_ofuncs) {
 			.ctor = _nvkm_connector_ctor,
 			.dtor = _nvkm_connector_dtor,
 			.init = _nvkm_connector_init,

drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.h

@@ -1,11 +1,13 @@
 #ifndef __NVKM_DISP_CONN_H__
 #define __NVKM_DISP_CONN_H__
-#include "priv.h"
-
+#include <core/object.h>
 #include <core/notify.h>
 
+#include <subdev/bios.h>
+#include <subdev/bios/conn.h>
+
 struct nvkm_connector {
-	struct nouveau_object base;
+	struct nvkm_object base;
 	struct list_head head;
 
 	struct nvbios_connE info;
@@ -29,19 +31,19 @@ struct nvkm_connector {
 	_nvkm_connector_fini(nv_object(disp), (s));                            \
 })
 
-int nvkm_connector_create_(struct nouveau_object *, struct nouveau_object *,
-			   struct nouveau_oclass *, struct nvbios_connE *,
+int nvkm_connector_create_(struct nvkm_object *, struct nvkm_object *,
+			   struct nvkm_oclass *, struct nvbios_connE *,
 			   int, int, void **);
 
-int  _nvkm_connector_ctor(struct nouveau_object *, struct nouveau_object *,
-			  struct nouveau_oclass *, void *, u32,
-			  struct nouveau_object **);
-void _nvkm_connector_dtor(struct nouveau_object *);
-int  _nvkm_connector_init(struct nouveau_object *);
-int  _nvkm_connector_fini(struct nouveau_object *, bool);
+int  _nvkm_connector_ctor(struct nvkm_object *, struct nvkm_object *,
+			  struct nvkm_oclass *, void *, u32,
+			  struct nvkm_object **);
+void _nvkm_connector_dtor(struct nvkm_object *);
+int  _nvkm_connector_init(struct nvkm_object *);
+int  _nvkm_connector_fini(struct nvkm_object *, bool);
 
 struct nvkm_connector_impl {
-	struct nouveau_oclass base;
+	struct nvkm_oclass base;
 };
 
 #ifndef MSG
@@ -53,5 +55,4 @@ struct nvkm_connector_impl {
 #define DBG(f,a...) MSG(debug, f, ##a)
 #define ERR(f,a...) MSG(error, f, ##a)
 #endif
-
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/dacnv50.c

@@ -21,16 +21,14 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
+#include "outp.h"
 
 #include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
 #include <subdev/timer.h>
 
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
 
 int
 nv50_dac_power(NV50_DISP_MTHD_V1)

drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.c

@@ -21,20 +21,16 @@
  *
  * Authors: Ben Skeggs
  */
+#include "dport.h"
+#include "outpdp.h"
+#include "nv50.h"
 
 #include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
 #include <subdev/bios/init.h>
 #include <subdev/i2c.h>
 
-#include "nv50.h"
-
 #include <nvif/class.h>
 
-#include "dport.h"
-#include "outpdp.h"
-
 /******************************************************************************
  * link training
  *****************************************************************************/
@@ -54,8 +50,8 @@ dp_set_link_config(struct dp_state *dp)
 {
 	struct nvkm_output_dp_impl *impl = (void *)nv_oclass(dp->outp);
 	struct nvkm_output_dp *outp = dp->outp;
-	struct nouveau_disp *disp = nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(disp);
+	struct nvkm_disp *disp = nvkm_disp(outp);
+	struct nvkm_bios *bios = nvkm_bios(disp);
 	struct nvbios_init init = {
 		.subdev = nv_subdev(disp),
 		.bios = bios,
@@ -264,8 +260,8 @@ static void
 dp_link_train_init(struct dp_state *dp, bool spread)
 {
 	struct nvkm_output_dp *outp = dp->outp;
-	struct nouveau_disp *disp = nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(disp);
+	struct nvkm_disp *disp = nvkm_disp(outp);
+	struct nvkm_bios *bios = nvkm_bios(disp);
 	struct nvbios_init init = {
 		.subdev = nv_subdev(disp),
 		.bios = bios,
@@ -290,8 +286,8 @@ static void
 dp_link_train_fini(struct dp_state *dp)
 {
 	struct nvkm_output_dp *outp = dp->outp;
-	struct nouveau_disp *disp = nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(disp);
+	struct nvkm_disp *disp = nvkm_disp(outp);
+	struct nvkm_bios *bios = nvkm_bios(disp);
 	struct nvbios_init init = {
 		.subdev = nv_subdev(disp),
 		.bios = bios,
@@ -309,7 +305,7 @@ static const struct dp_rates {
 	u32 rate;
 	u8  bw;
 	u8  nr;
-} nouveau_dp_rates[] = {
+} nvkm_dp_rates[] = {
 	{ 2160000, 0x14, 4 },
 	{ 1080000, 0x0a, 4 },
 	{ 1080000, 0x14, 2 },
@@ -323,11 +319,11 @@ static const struct dp_rates {
 };
 
 void
-nouveau_dp_train(struct work_struct *w)
+nvkm_dp_train(struct work_struct *w)
 {
 	struct nvkm_output_dp *outp = container_of(w, typeof(*outp), lt.work);
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const struct dp_rates *cfg = nouveau_dp_rates;
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+	const struct dp_rates *cfg = nvkm_dp_rates;
 	struct dp_state _dp = {
 		.outp = outp,
 	}, *dp = &_dp;

drivers/gpu/drm/nouveau/nvkm/engine/disp/dport.h

@@ -1,5 +1,6 @@
 #ifndef __NVKM_DISP_DPORT_H__
 #define __NVKM_DISP_DPORT_H__
+#include <core/os.h>
 
 /* DPCD Receiver Capabilities */
 #define DPCD_RC00_DPCD_REV                                              0x00000
@@ -70,6 +71,5 @@
 #define DPCD_LS0C_LANE1_POST_CURSOR2                                       0x0c
 #define DPCD_LS0C_LANE0_POST_CURSOR2                                       0x03
 
-void nouveau_dp_train(struct work_struct *);
-
+void nvkm_dp_train(struct work_struct *);
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv84.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.c

@@ -21,20 +21,16 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
 
 #include <nvif/class.h>
 
-#include "nv50.h"
-
 /*******************************************************************************
  * EVO master channel object
  ******************************************************************************/
 
 const struct nv50_disp_mthd_list
-nv84_disp_core_mthd_dac = {
+g84_disp_core_mthd_dac = {
 	.mthd = 0x0080,
 	.addr = 0x000008,
 	.data = {
@@ -46,7 +42,7 @@ nv84_disp_core_mthd_dac = {
 };
 
 const struct nv50_disp_mthd_list
-nv84_disp_core_mthd_head = {
+g84_disp_core_mthd_head = {
 	.mthd = 0x0400,
 	.addr = 0x000540,
 	.data = {
@@ -98,15 +94,15 @@ nv84_disp_core_mthd_head = {
 };
 
 const struct nv50_disp_mthd_chan
-nv84_disp_core_mthd_chan = {
+g84_disp_core_mthd_chan = {
 	.name = "Core",
 	.addr = 0x000000,
 	.data = {
 		{ "Global", 1, &nv50_disp_core_mthd_base },
-		{    "DAC", 3, &nv84_disp_core_mthd_dac  },
+		{    "DAC", 3, &g84_disp_core_mthd_dac  },
 		{    "SOR", 2, &nv50_disp_core_mthd_sor  },
 		{   "PIOR", 3, &nv50_disp_core_mthd_pior },
-		{   "HEAD", 2, &nv84_disp_core_mthd_head },
+		{   "HEAD", 2, &g84_disp_core_mthd_head },
 		{}
 	}
 };
@@ -116,7 +112,7 @@ nv84_disp_core_mthd_chan = {
  ******************************************************************************/
 
 static const struct nv50_disp_mthd_list
-nv84_disp_base_mthd_base = {
+g84_disp_base_mthd_base = {
 	.mthd = 0x0000,
 	.addr = 0x000000,
 	.data = {
@@ -146,11 +142,11 @@ nv84_disp_base_mthd_base = {
 };
 
 const struct nv50_disp_mthd_chan
-nv84_disp_base_mthd_chan = {
+g84_disp_base_mthd_chan = {
 	.name = "Base",
 	.addr = 0x000540,
 	.data = {
-		{ "Global", 1, &nv84_disp_base_mthd_base },
+		{ "Global", 1, &g84_disp_base_mthd_base },
 		{  "Image", 2, &nv50_disp_base_mthd_image },
 		{}
 	}
@@ -161,7 +157,7 @@ nv84_disp_base_mthd_chan = {
  ******************************************************************************/
 
 static const struct nv50_disp_mthd_list
-nv84_disp_ovly_mthd_base = {
+g84_disp_ovly_mthd_base = {
 	.mthd = 0x0000,
 	.addr = 0x000000,
 	.data = {
@@ -189,11 +185,11 @@ nv84_disp_ovly_mthd_base = {
 };
 
 const struct nv50_disp_mthd_chan
-nv84_disp_ovly_mthd_chan = {
+g84_disp_ovly_mthd_chan = {
 	.name = "Overlay",
 	.addr = 0x000540,
 	.data = {
-		{ "Global", 1, &nv84_disp_ovly_mthd_base },
+		{ "Global", 1, &g84_disp_ovly_mthd_base },
 		{}
 	}
 };
@@ -202,8 +198,8 @@ nv84_disp_ovly_mthd_chan = {
  * Base display object
  ******************************************************************************/
 
-static struct nouveau_oclass
-nv84_disp_sclass[] = {
+static struct nvkm_oclass
+g84_disp_sclass[] = {
 	{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
 	{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
 	{ G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
@@ -212,8 +208,8 @@ nv84_disp_sclass[] = {
 	{}
 };
 
-static struct nouveau_oclass
-nv84_disp_main_oclass[] = {
+static struct nvkm_oclass
+g84_disp_main_oclass[] = {
 	{ G82_DISP, &nv50_disp_main_ofuncs },
 	{}
 };
@@ -223,15 +219,15 @@ nv84_disp_main_oclass[] = {
  ******************************************************************************/
 
 static int
-nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
+g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+	      struct nvkm_oclass *oclass, void *data, u32 size,
+	      struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv;
 	int ret;
 
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
-				  "display", &priv);
+	ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
+			       "display", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -240,11 +236,11 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	if (ret)
 		return ret;
 
-	nv_engine(priv)->sclass = nv84_disp_main_oclass;
+	nv_engine(priv)->sclass = g84_disp_main_oclass;
 	nv_engine(priv)->cclass = &nv50_disp_cclass;
 	nv_subdev(priv)->intr = nv50_disp_intr;
 	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
-	priv->sclass = nv84_disp_sclass;
+	priv->sclass = g84_disp_sclass;
 	priv->head.nr = 2;
 	priv->dac.nr = 3;
 	priv->sor.nr = 2;
@@ -252,25 +248,25 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	priv->dac.power = nv50_dac_power;
 	priv->dac.sense = nv50_dac_sense;
 	priv->sor.power = nv50_sor_power;
-	priv->sor.hdmi = nv84_hdmi_ctrl;
+	priv->sor.hdmi = g84_hdmi_ctrl;
 	priv->pior.power = nv50_pior_power;
 	return 0;
 }
 
-struct nouveau_oclass *
-nv84_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+g84_disp_oclass = &(struct nv50_disp_impl) {
 	.base.base.handle = NV_ENGINE(DISP, 0x82),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv84_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
+		.ctor = g84_disp_ctor,
+		.dtor = _nvkm_disp_dtor,
+		.init = _nvkm_disp_init,
+		.fini = _nvkm_disp_fini,
 	},
 	.base.vblank = &nv50_disp_vblank_func,
 	.base.outp =  nv50_disp_outp_sclass,
-	.mthd.core = &nv84_disp_core_mthd_chan,
-	.mthd.base = &nv84_disp_base_mthd_chan,
-	.mthd.ovly = &nv84_disp_ovly_mthd_chan,
+	.mthd.core = &g84_disp_core_mthd_chan,
+	.mthd.base = &g84_disp_base_mthd_chan,
+	.mthd.ovly = &g84_disp_ovly_mthd_chan,
 	.mthd.prev = 0x000004,
 	.head.scanoutpos = nv50_disp_main_scanoutpos,
 }.base.base;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv94.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.c

@@ -21,20 +21,17 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
+#include "outpdp.h"
 
 #include <nvif/class.h>
 
-#include "nv50.h"
-
 /*******************************************************************************
  * EVO master channel object
  ******************************************************************************/
 
 const struct nv50_disp_mthd_list
-nv94_disp_core_mthd_sor = {
+g94_disp_core_mthd_sor = {
 	.mthd = 0x0040,
 	.addr = 0x000008,
 	.data = {
@@ -44,15 +41,15 @@ nv94_disp_core_mthd_sor = {
 };
 
 const struct nv50_disp_mthd_chan
-nv94_disp_core_mthd_chan = {
+g94_disp_core_mthd_chan = {
 	.name = "Core",
 	.addr = 0x000000,
 	.data = {
 		{ "Global", 1, &nv50_disp_core_mthd_base },
-		{    "DAC", 3, &nv84_disp_core_mthd_dac  },
-		{    "SOR", 4, &nv94_disp_core_mthd_sor  },
+		{    "DAC", 3, &g84_disp_core_mthd_dac  },
+		{    "SOR", 4, &g94_disp_core_mthd_sor  },
 		{   "PIOR", 3, &nv50_disp_core_mthd_pior },
-		{   "HEAD", 2, &nv84_disp_core_mthd_head },
+		{   "HEAD", 2, &g84_disp_core_mthd_head },
 		{}
 	}
 };
@@ -61,8 +58,8 @@ nv94_disp_core_mthd_chan = {
  * Base display object
  ******************************************************************************/
 
-static struct nouveau_oclass
-nv94_disp_sclass[] = {
+static struct nvkm_oclass
+g94_disp_sclass[] = {
 	{ GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
 	{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
 	{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
@@ -71,8 +68,8 @@ nv94_disp_sclass[] = {
 	{}
 };
 
-static struct nouveau_oclass
-nv94_disp_main_oclass[] = {
+static struct nvkm_oclass
+g94_disp_main_oclass[] = {
 	{ GT206_DISP, &nv50_disp_main_ofuncs },
 	{}
 };
@@ -82,15 +79,15 @@ nv94_disp_main_oclass[] = {
  ******************************************************************************/
 
 static int
-nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
+g94_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+	      struct nvkm_oclass *oclass, void *data, u32 size,
+	      struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv;
 	int ret;
 
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
-				  "display", &priv);
+	ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
+			       "display", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -99,11 +96,11 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	if (ret)
 		return ret;
 
-	nv_engine(priv)->sclass = nv94_disp_main_oclass;
+	nv_engine(priv)->sclass = g94_disp_main_oclass;
 	nv_engine(priv)->cclass = &nv50_disp_cclass;
 	nv_subdev(priv)->intr = nv50_disp_intr;
 	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
-	priv->sclass = nv94_disp_sclass;
+	priv->sclass = g94_disp_sclass;
 	priv->head.nr = 2;
 	priv->dac.nr = 3;
 	priv->sor.nr = 4;
@@ -111,32 +108,32 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	priv->dac.power = nv50_dac_power;
 	priv->dac.sense = nv50_dac_sense;
 	priv->sor.power = nv50_sor_power;
-	priv->sor.hdmi = nv84_hdmi_ctrl;
+	priv->sor.hdmi = g84_hdmi_ctrl;
 	priv->pior.power = nv50_pior_power;
 	return 0;
 }
 
-struct nouveau_oclass *
-nv94_disp_outp_sclass[] = {
+struct nvkm_oclass *
+g94_disp_outp_sclass[] = {
 	&nv50_pior_dp_impl.base.base,
-	&nv94_sor_dp_impl.base.base,
+	&g94_sor_dp_impl.base.base,
 	NULL
 };
 
-struct nouveau_oclass *
-nv94_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+g94_disp_oclass = &(struct nv50_disp_impl) {
 	.base.base.handle = NV_ENGINE(DISP, 0x88),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nv94_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
+		.ctor = g94_disp_ctor,
+		.dtor = _nvkm_disp_dtor,
+		.init = _nvkm_disp_init,
+		.fini = _nvkm_disp_fini,
 	},
 	.base.vblank = &nv50_disp_vblank_func,
-	.base.outp =  nv94_disp_outp_sclass,
-	.mthd.core = &nv94_disp_core_mthd_chan,
-	.mthd.base = &nv84_disp_base_mthd_chan,
-	.mthd.ovly = &nv84_disp_ovly_mthd_chan,
+	.base.outp =  g94_disp_outp_sclass,
+	.mthd.core = &g94_disp_core_mthd_chan,
+	.mthd.base = &g84_disp_base_mthd_chan,
+	.mthd.ovly = &g84_disp_ovly_mthd_chan,
 	.mthd.prev = 0x000004,
 	.head.scanoutpos = nv50_disp_main_scanoutpos,
 }.base.base;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nvd0.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/gf110.c

@@ -21,33 +21,30 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
+#include "outp.h"
+#include "outpdp.h"
 
-#include <core/object.h>
 #include <core/client.h>
-#include <core/parent.h>
-#include <core/handle.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <engine/disp.h>
-
+#include <core/gpuobj.h>
+#include <core/ramht.h>
 #include <subdev/bios.h>
 #include <subdev/bios/dcb.h>
 #include <subdev/bios/disp.h>
 #include <subdev/bios/init.h>
 #include <subdev/bios/pll.h>
 #include <subdev/devinit.h>
-#include <subdev/fb.h>
 #include <subdev/timer.h>
 
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
 
 /*******************************************************************************
  * EVO channel base class
  ******************************************************************************/
 
 static void
-nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
+gf110_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
 {
 	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
 	nv_mask(priv, 0x610090, 0x00000001 << index, 0x00000000 << index);
@@ -55,7 +52,7 @@ nvd0_disp_chan_uevent_fini(struct nvkm_event *event, int type, int index)
 }
 
 static void
-nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
+gf110_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
 {
 	struct nv50_disp_priv *priv = container_of(event, typeof(*priv), uevent);
 	nv_wr32(priv, 0x61008c, 0x00000001 << index);
@@ -63,10 +60,10 @@ nvd0_disp_chan_uevent_init(struct nvkm_event *event, int types, int index)
 }
 
 const struct nvkm_event_func
-nvd0_disp_chan_uevent = {
+gf110_disp_chan_uevent = {
 	.ctor = nv50_disp_chan_uevent_ctor,
-	.init = nvd0_disp_chan_uevent_init,
-	.fini = nvd0_disp_chan_uevent_fini,
+	.init = gf110_disp_chan_uevent_init,
+	.fini = gf110_disp_chan_uevent_fini,
 };
 
 /*******************************************************************************
@@ -74,25 +71,25 @@ nvd0_disp_chan_uevent = {
  ******************************************************************************/
 
 static int
-nvd0_disp_dmac_object_attach(struct nouveau_object *parent,
-			     struct nouveau_object *object, u32 name)
+gf110_disp_dmac_object_attach(struct nvkm_object *parent,
+			      struct nvkm_object *object, u32 name)
 {
 	struct nv50_disp_base *base = (void *)parent->parent;
 	struct nv50_disp_chan *chan = (void *)parent;
 	u32 addr = nv_gpuobj(object)->node->offset;
 	u32 data = (chan->chid << 27) | (addr << 9) | 0x00000001;
-	return nouveau_ramht_insert(base->ramht, chan->chid, name, data);
+	return nvkm_ramht_insert(base->ramht, chan->chid, name, data);
 }
 
 static void
-nvd0_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
+gf110_disp_dmac_object_detach(struct nvkm_object *parent, int cookie)
 {
 	struct nv50_disp_base *base = (void *)parent->parent;
-	nouveau_ramht_remove(base->ramht, cookie);
+	nvkm_ramht_remove(base->ramht, cookie);
 }
 
 static int
-nvd0_disp_dmac_init(struct nouveau_object *object)
+gf110_disp_dmac_init(struct nvkm_object *object)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_dmac *dmac = (void *)object;
@@ -125,7 +122,7 @@ nvd0_disp_dmac_init(struct nouveau_object *object)
 }
 
 static int
-nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
+gf110_disp_dmac_fini(struct nvkm_object *object, bool suspend)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_dmac *dmac = (void *)object;
@@ -153,7 +150,7 @@ nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
  ******************************************************************************/
 
 const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_base = {
+gf110_disp_core_mthd_base = {
 	.mthd = 0x0000,
 	.addr = 0x000000,
 	.data = {
@@ -166,7 +163,7 @@ nvd0_disp_core_mthd_base = {
 };
 
 const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_dac = {
+gf110_disp_core_mthd_dac = {
 	.mthd = 0x0020,
 	.addr = 0x000020,
 	.data = {
@@ -179,7 +176,7 @@ nvd0_disp_core_mthd_dac = {
 };
 
 const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_sor = {
+gf110_disp_core_mthd_sor = {
 	.mthd = 0x0020,
 	.addr = 0x000020,
 	.data = {
@@ -192,7 +189,7 @@ nvd0_disp_core_mthd_sor = {
 };
 
 const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_pior = {
+gf110_disp_core_mthd_pior = {
 	.mthd = 0x0020,
 	.addr = 0x000020,
 	.data = {
@@ -205,7 +202,7 @@ nvd0_disp_core_mthd_pior = {
 };
 
 static const struct nv50_disp_mthd_list
-nvd0_disp_core_mthd_head = {
+gf110_disp_core_mthd_head = {
 	.mthd = 0x0300,
 	.addr = 0x000300,
 	.data = {
@@ -279,21 +276,21 @@ nvd0_disp_core_mthd_head = {
 };
 
 static const struct nv50_disp_mthd_chan
-nvd0_disp_core_mthd_chan = {
+gf110_disp_core_mthd_chan = {
 	.name = "Core",
 	.addr = 0x000000,
 	.data = {
-		{ "Global", 1, &nvd0_disp_core_mthd_base },
-		{    "DAC", 3, &nvd0_disp_core_mthd_dac  },
-		{    "SOR", 8, &nvd0_disp_core_mthd_sor  },
-		{   "PIOR", 4, &nvd0_disp_core_mthd_pior },
-		{   "HEAD", 4, &nvd0_disp_core_mthd_head },
+		{ "Global", 1, &gf110_disp_core_mthd_base },
+		{    "DAC", 3, &gf110_disp_core_mthd_dac  },
+		{    "SOR", 8, &gf110_disp_core_mthd_sor  },
+		{   "PIOR", 4, &gf110_disp_core_mthd_pior },
+		{   "HEAD", 4, &gf110_disp_core_mthd_head },
 		{}
 	}
 };
 
 static int
-nvd0_disp_core_init(struct nouveau_object *object)
+gf110_disp_core_init(struct nvkm_object *object)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_dmac *mast = (void *)object;
@@ -324,7 +321,7 @@ nvd0_disp_core_init(struct nouveau_object *object)
 }
 
 static int
-nvd0_disp_core_fini(struct nouveau_object *object, bool suspend)
+gf110_disp_core_fini(struct nvkm_object *object, bool suspend)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_dmac *mast = (void *)object;
@@ -346,18 +343,18 @@ nvd0_disp_core_fini(struct nouveau_object *object, bool suspend)
 }
 
 struct nv50_disp_chan_impl
-nvd0_disp_core_ofuncs = {
+gf110_disp_core_ofuncs = {
 	.base.ctor = nv50_disp_core_ctor,
 	.base.dtor = nv50_disp_dmac_dtor,
-	.base.init = nvd0_disp_core_init,
-	.base.fini = nvd0_disp_core_fini,
+	.base.init = gf110_disp_core_init,
+	.base.fini = gf110_disp_core_fini,
 	.base.ntfy = nv50_disp_chan_ntfy,
 	.base.map  = nv50_disp_chan_map,
 	.base.rd32 = nv50_disp_chan_rd32,
 	.base.wr32 = nv50_disp_chan_wr32,
 	.chid = 0,
-	.attach = nvd0_disp_dmac_object_attach,
-	.detach = nvd0_disp_dmac_object_detach,
+	.attach = gf110_disp_dmac_object_attach,
+	.detach = gf110_disp_dmac_object_detach,
 };
 
 /*******************************************************************************
@@ -365,7 +362,7 @@ nvd0_disp_core_ofuncs = {
  ******************************************************************************/
 
 static const struct nv50_disp_mthd_list
-nvd0_disp_base_mthd_base = {
+gf110_disp_base_mthd_base = {
 	.mthd = 0x0000,
 	.addr = 0x000000,
 	.data = {
@@ -415,7 +412,7 @@ nvd0_disp_base_mthd_base = {
 };
 
 static const struct nv50_disp_mthd_list
-nvd0_disp_base_mthd_image = {
+gf110_disp_base_mthd_image = {
 	.mthd = 0x0400,
 	.addr = 0x000400,
 	.data = {
@@ -429,29 +426,29 @@ nvd0_disp_base_mthd_image = {
 };
 
 const struct nv50_disp_mthd_chan
-nvd0_disp_base_mthd_chan = {
+gf110_disp_base_mthd_chan = {
 	.name = "Base",
 	.addr = 0x001000,
 	.data = {
-		{ "Global", 1, &nvd0_disp_base_mthd_base },
-		{  "Image", 2, &nvd0_disp_base_mthd_image },
+		{ "Global", 1, &gf110_disp_base_mthd_base },
+		{  "Image", 2, &gf110_disp_base_mthd_image },
 		{}
 	}
 };
 
 struct nv50_disp_chan_impl
-nvd0_disp_base_ofuncs = {
+gf110_disp_base_ofuncs = {
 	.base.ctor = nv50_disp_base_ctor,
 	.base.dtor = nv50_disp_dmac_dtor,
-	.base.init = nvd0_disp_dmac_init,
-	.base.fini = nvd0_disp_dmac_fini,
+	.base.init = gf110_disp_dmac_init,
+	.base.fini = gf110_disp_dmac_fini,
 	.base.ntfy = nv50_disp_chan_ntfy,
 	.base.map  = nv50_disp_chan_map,
 	.base.rd32 = nv50_disp_chan_rd32,
 	.base.wr32 = nv50_disp_chan_wr32,
 	.chid = 1,
-	.attach = nvd0_disp_dmac_object_attach,
-	.detach = nvd0_disp_dmac_object_detach,
+	.attach = gf110_disp_dmac_object_attach,
+	.detach = gf110_disp_dmac_object_detach,
 };
 
 /*******************************************************************************
@@ -459,7 +456,7 @@ nvd0_disp_base_ofuncs = {
  ******************************************************************************/
 
 static const struct nv50_disp_mthd_list
-nvd0_disp_ovly_mthd_base = {
+gf110_disp_ovly_mthd_base = {
 	.mthd = 0x0000,
 	.data = {
 		{ 0x0080, 0x665080 },
@@ -511,28 +508,28 @@ nvd0_disp_ovly_mthd_base = {
 };
 
 static const struct nv50_disp_mthd_chan
-nvd0_disp_ovly_mthd_chan = {
+gf110_disp_ovly_mthd_chan = {
 	.name = "Overlay",
 	.addr = 0x001000,
 	.data = {
-		{ "Global", 1, &nvd0_disp_ovly_mthd_base },
+		{ "Global", 1, &gf110_disp_ovly_mthd_base },
 		{}
 	}
 };
 
 struct nv50_disp_chan_impl
-nvd0_disp_ovly_ofuncs = {
+gf110_disp_ovly_ofuncs = {
 	.base.ctor = nv50_disp_ovly_ctor,
 	.base.dtor = nv50_disp_dmac_dtor,
-	.base.init = nvd0_disp_dmac_init,
-	.base.fini = nvd0_disp_dmac_fini,
+	.base.init = gf110_disp_dmac_init,
+	.base.fini = gf110_disp_dmac_fini,
 	.base.ntfy = nv50_disp_chan_ntfy,
 	.base.map  = nv50_disp_chan_map,
 	.base.rd32 = nv50_disp_chan_rd32,
 	.base.wr32 = nv50_disp_chan_wr32,
 	.chid = 5,
-	.attach = nvd0_disp_dmac_object_attach,
-	.detach = nvd0_disp_dmac_object_detach,
+	.attach = gf110_disp_dmac_object_attach,
+	.detach = gf110_disp_dmac_object_detach,
 };
 
 /*******************************************************************************
@@ -540,7 +537,7 @@ nvd0_disp_ovly_ofuncs = {
  ******************************************************************************/
 
 static int
-nvd0_disp_pioc_init(struct nouveau_object *object)
+gf110_disp_pioc_init(struct nvkm_object *object)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_pioc *pioc = (void *)object;
@@ -566,7 +563,7 @@ nvd0_disp_pioc_init(struct nouveau_object *object)
 }
 
 static int
-nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend)
+gf110_disp_pioc_fini(struct nvkm_object *object, bool suspend)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_pioc *pioc = (void *)object;
@@ -592,11 +589,11 @@ nvd0_disp_pioc_fini(struct nouveau_object *object, bool suspend)
  ******************************************************************************/
 
 struct nv50_disp_chan_impl
-nvd0_disp_oimm_ofuncs = {
+gf110_disp_oimm_ofuncs = {
 	.base.ctor = nv50_disp_oimm_ctor,
 	.base.dtor = nv50_disp_pioc_dtor,
-	.base.init = nvd0_disp_pioc_init,
-	.base.fini = nvd0_disp_pioc_fini,
+	.base.init = gf110_disp_pioc_init,
+	.base.fini = gf110_disp_pioc_fini,
 	.base.ntfy = nv50_disp_chan_ntfy,
 	.base.map  = nv50_disp_chan_map,
 	.base.rd32 = nv50_disp_chan_rd32,
@@ -609,11 +606,11 @@ nvd0_disp_oimm_ofuncs = {
  ******************************************************************************/
 
 struct nv50_disp_chan_impl
-nvd0_disp_curs_ofuncs = {
+gf110_disp_curs_ofuncs = {
 	.base.ctor = nv50_disp_curs_ctor,
 	.base.dtor = nv50_disp_pioc_dtor,
-	.base.init = nvd0_disp_pioc_init,
-	.base.fini = nvd0_disp_pioc_fini,
+	.base.init = gf110_disp_pioc_init,
+	.base.fini = gf110_disp_pioc_fini,
 	.base.ntfy = nv50_disp_chan_ntfy,
 	.base.map  = nv50_disp_chan_map,
 	.base.rd32 = nv50_disp_chan_rd32,
@@ -626,7 +623,7 @@ nvd0_disp_curs_ofuncs = {
  ******************************************************************************/
 
 int
-nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
+gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
 {
 	const u32 total  = nv_rd32(priv, 0x640414 + (head * 0x300));
 	const u32 blanke = nv_rd32(priv, 0x64041c + (head * 0x300));
@@ -658,14 +655,14 @@ nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
 }
 
 static int
-nvd0_disp_main_init(struct nouveau_object *object)
+gf110_disp_main_init(struct nvkm_object *object)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_base *base = (void *)object;
 	int ret, i;
 	u32 tmp;
 
-	ret = nouveau_parent_init(&base->base);
+	ret = nvkm_parent_init(&base->base);
 	if (ret)
 		return ret;
 
@@ -715,7 +712,7 @@ nvd0_disp_main_init(struct nouveau_object *object)
 	nv_wr32(priv, 0x6100b0, 0x00000307);
 
 	/* disable underflow reporting, preventing an intermittent issue
-	 * on some nve4 boards where the production vbios left this
+	 * on some gk104 boards where the production vbios left this
 	 * setting enabled by default.
 	 *
 	 * ftp://download.nvidia.com/open-gpu-doc/gk104-disable-underflow-reporting/1/gk104-disable-underflow-reporting.txt
@@ -727,7 +724,7 @@ nvd0_disp_main_init(struct nouveau_object *object)
 }
 
 static int
-nvd0_disp_main_fini(struct nouveau_object *object, bool suspend)
+gf110_disp_main_fini(struct nvkm_object *object, bool suspend)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_base *base = (void *)object;
@@ -735,32 +732,32 @@ nvd0_disp_main_fini(struct nouveau_object *object, bool suspend)
 	/* disable all interrupts */
 	nv_wr32(priv, 0x6100b0, 0x00000000);
 
-	return nouveau_parent_fini(&base->base, suspend);
+	return nvkm_parent_fini(&base->base, suspend);
 }
 
-struct nouveau_ofuncs
-nvd0_disp_main_ofuncs = {
+struct nvkm_ofuncs
+gf110_disp_main_ofuncs = {
 	.ctor = nv50_disp_main_ctor,
 	.dtor = nv50_disp_main_dtor,
-	.init = nvd0_disp_main_init,
-	.fini = nvd0_disp_main_fini,
+	.init = gf110_disp_main_init,
+	.fini = gf110_disp_main_fini,
 	.mthd = nv50_disp_main_mthd,
-	.ntfy = nouveau_disp_ntfy,
+	.ntfy = nvkm_disp_ntfy,
 };
 
-static struct nouveau_oclass
-nvd0_disp_main_oclass[] = {
-	{ GF110_DISP, &nvd0_disp_main_ofuncs },
+static struct nvkm_oclass
+gf110_disp_main_oclass[] = {
+	{ GF110_DISP, &gf110_disp_main_ofuncs },
 	{}
 };
 
-static struct nouveau_oclass
-nvd0_disp_sclass[] = {
-	{ GF110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
-	{ GF110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
-	{ GF110_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
-	{ GF110_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
-	{ GF110_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
+static struct nvkm_oclass
+gf110_disp_sclass[] = {
+	{ GF110_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
+	{ GF110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
+	{ GF110_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
+	{ GF110_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
+	{ GF110_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
 	{}
 };
 
@@ -769,24 +766,24 @@ nvd0_disp_sclass[] = {
  ******************************************************************************/
 
 static void
-nvd0_disp_vblank_init(struct nvkm_event *event, int type, int head)
+gf110_disp_vblank_init(struct nvkm_event *event, int type, int head)
 {
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+	struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
 	nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000001);
 }
 
 static void
-nvd0_disp_vblank_fini(struct nvkm_event *event, int type, int head)
+gf110_disp_vblank_fini(struct nvkm_event *event, int type, int head)
 {
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+	struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
 	nv_mask(disp, 0x6100c0 + (head * 0x800), 0x00000001, 0x00000000);
 }
 
 const struct nvkm_event_func
-nvd0_disp_vblank_func = {
-	.ctor = nouveau_disp_vblank_ctor,
-	.init = nvd0_disp_vblank_init,
-	.fini = nvd0_disp_vblank_fini,
+gf110_disp_vblank_func = {
+	.ctor = nvkm_disp_vblank_ctor,
+	.init = gf110_disp_vblank_init,
+	.fini = gf110_disp_vblank_fini,
 };
 
 static struct nvkm_output *
@@ -794,7 +791,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl,
 	    u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
 	    struct nvbios_outp *info)
 {
-	struct nouveau_bios *bios = nouveau_bios(priv);
+	struct nvkm_bios *bios = nvkm_bios(priv);
 	struct nvkm_output *outp;
 	u16 mask, type;
 
@@ -838,7 +835,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl,
 static struct nvkm_output *
 exec_script(struct nv50_disp_priv *priv, int head, int id)
 {
-	struct nouveau_bios *bios = nouveau_bios(priv);
+	struct nvkm_bios *bios = nvkm_bios(priv);
 	struct nvkm_output *outp;
 	struct nvbios_outp info;
 	u8  ver, hdr, cnt, len;
@@ -874,7 +871,7 @@ exec_script(struct nv50_disp_priv *priv, int head, int id)
 static struct nvkm_output *
 exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf)
 {
-	struct nouveau_bios *bios = nouveau_bios(priv);
+	struct nvkm_bios *bios = nvkm_bios(priv);
 	struct nvkm_output *outp;
 	struct nvbios_outp info1;
 	struct nvbios_ocfg info2;
@@ -934,13 +931,13 @@ exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf)
 }
 
 static void
-nvd0_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head)
+gf110_disp_intr_unk1_0(struct nv50_disp_priv *priv, int head)
 {
 	exec_script(priv, head, 1);
 }
 
 static void
-nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
+gf110_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
 {
 	struct nvkm_output *outp = exec_script(priv, head, 2);
 
@@ -949,7 +946,7 @@ nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
 		struct nvkm_output_dp *outpdp = (void *)outp;
 		struct nvbios_init init = {
 			.subdev = nv_subdev(priv),
-			.bios = nouveau_bios(priv),
+			.bios = nvkm_bios(priv),
 			.outp = &outp->info,
 			.crtc = head,
 			.offset = outpdp->info.script[4],
@@ -962,9 +959,9 @@ nvd0_disp_intr_unk2_0(struct nv50_disp_priv *priv, int head)
 }
 
 static void
-nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head)
+gf110_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head)
 {
-	struct nouveau_devinit *devinit = nouveau_devinit(priv);
+	struct nvkm_devinit *devinit = nvkm_devinit(priv);
 	u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
 	if (pclk)
 		devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
@@ -972,8 +969,8 @@ nvd0_disp_intr_unk2_1(struct nv50_disp_priv *priv, int head)
 }
 
 static void
-nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
-			 struct dcb_output *outp)
+gf110_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
+			  struct dcb_output *outp)
 {
 	const int or = ffs(outp->or) - 1;
 	const u32 ctrl = nv_rd32(priv, 0x660200 + (or   * 0x020));
@@ -1033,7 +1030,7 @@ nvd0_disp_intr_unk2_2_tu(struct nv50_disp_priv *priv, int head,
 }
 
 static void
-nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
+gf110_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
 {
 	struct nvkm_output *outp;
 	u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
@@ -1075,7 +1072,7 @@ nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
 			nv_mask(priv, addr, 0x007c0000, 0x00280000);
 			break;
 		case DCB_OUTPUT_DP:
-			nvd0_disp_intr_unk2_2_tu(priv, head, &outp->info);
+			gf110_disp_intr_unk2_2_tu(priv, head, &outp->info);
 			break;
 		default:
 			break;
@@ -1086,7 +1083,7 @@ nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
 }
 
 static void
-nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head)
+gf110_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head)
 {
 	u32 pclk = nv_rd32(priv, 0x660450 + (head * 0x300)) / 1000;
 	u32 conf;
@@ -1095,7 +1092,7 @@ nvd0_disp_intr_unk4_0(struct nv50_disp_priv *priv, int head)
 }
 
 void
-nvd0_disp_intr_supervisor(struct work_struct *work)
+gf110_disp_intr_supervisor(struct work_struct *work)
 {
 	struct nv50_disp_priv *priv =
 		container_of(work, struct nv50_disp_priv, supervisor);
@@ -1115,7 +1112,7 @@ nvd0_disp_intr_supervisor(struct work_struct *work)
 			if (!(mask[head] & 0x00001000))
 				continue;
 			nv_debug(priv, "supervisor 1.0 - head %d\n", head);
-			nvd0_disp_intr_unk1_0(priv, head);
+			gf110_disp_intr_unk1_0(priv, head);
 		}
 	} else
 	if (priv->super & 0x00000002) {
@@ -1123,19 +1120,19 @@ nvd0_disp_intr_supervisor(struct work_struct *work)
 			if (!(mask[head] & 0x00001000))
 				continue;
 			nv_debug(priv, "supervisor 2.0 - head %d\n", head);
-			nvd0_disp_intr_unk2_0(priv, head);
+			gf110_disp_intr_unk2_0(priv, head);
 		}
 		for (head = 0; head < priv->head.nr; head++) {
 			if (!(mask[head] & 0x00010000))
 				continue;
 			nv_debug(priv, "supervisor 2.1 - head %d\n", head);
-			nvd0_disp_intr_unk2_1(priv, head);
+			gf110_disp_intr_unk2_1(priv, head);
 		}
 		for (head = 0; head < priv->head.nr; head++) {
 			if (!(mask[head] & 0x00001000))
 				continue;
 			nv_debug(priv, "supervisor 2.2 - head %d\n", head);
-			nvd0_disp_intr_unk2_2(priv, head);
+			gf110_disp_intr_unk2_2(priv, head);
 		}
 	} else
 	if (priv->super & 0x00000004) {
@@ -1143,7 +1140,7 @@ nvd0_disp_intr_supervisor(struct work_struct *work)
 			if (!(mask[head] & 0x00001000))
 				continue;
 			nv_debug(priv, "supervisor 3.0 - head %d\n", head);
-			nvd0_disp_intr_unk4_0(priv, head);
+			gf110_disp_intr_unk4_0(priv, head);
 		}
 	}
 
@@ -1153,7 +1150,7 @@ nvd0_disp_intr_supervisor(struct work_struct *work)
 }
 
 static void
-nvd0_disp_intr_error(struct nv50_disp_priv *priv, int chid)
+gf110_disp_intr_error(struct nv50_disp_priv *priv, int chid)
 {
 	const struct nv50_disp_impl *impl = (void *)nv_object(priv)->oclass;
 	u32 mthd = nv_rd32(priv, 0x6101f0 + (chid * 12));
@@ -1200,7 +1197,7 @@ nvd0_disp_intr_error(struct nv50_disp_priv *priv, int chid)
 }
 
 void
-nvd0_disp_intr(struct nouveau_subdev *subdev)
+gf110_disp_intr(struct nvkm_subdev *subdev)
 {
 	struct nv50_disp_priv *priv = (void *)subdev;
 	u32 intr = nv_rd32(priv, 0x610088);
@@ -1220,7 +1217,7 @@ nvd0_disp_intr(struct nouveau_subdev *subdev)
 		u32 stat = nv_rd32(priv, 0x61009c);
 		int chid = ffs(stat) - 1;
 		if (chid >= 0)
-			nvd0_disp_intr_error(priv, chid);
+			gf110_disp_intr_error(priv, chid);
 		intr &= ~0x00000002;
 	}
 
@@ -1246,7 +1243,7 @@ nvd0_disp_intr(struct nouveau_subdev *subdev)
 		if (mask & intr) {
 			u32 stat = nv_rd32(priv, 0x6100bc + (i * 0x800));
 			if (stat & 0x00000001)
-				nouveau_disp_vblank(&priv->base, i);
+				nvkm_disp_vblank(&priv->base, i);
 			nv_mask(priv, 0x6100bc + (i * 0x800), 0, 0);
 			nv_rd32(priv, 0x6100c0 + (i * 0x800));
 		}
@@ -1254,60 +1251,60 @@ nvd0_disp_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
+gf110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+		struct nvkm_oclass *oclass, void *data, u32 size,
+		struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv;
 	int heads = nv_rd32(parent, 0x022448);
 	int ret;
 
-	ret = nouveau_disp_create(parent, engine, oclass, heads,
-				  "PDISP", "display", &priv);
+	ret = nvkm_disp_create(parent, engine, oclass, heads,
+			       "PDISP", "display", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
-	ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+	ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
 	if (ret)
 		return ret;
 
-	nv_engine(priv)->sclass = nvd0_disp_main_oclass;
+	nv_engine(priv)->sclass = gf110_disp_main_oclass;
 	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nvd0_disp_intr;
-	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
-	priv->sclass = nvd0_disp_sclass;
+	nv_subdev(priv)->intr = gf110_disp_intr;
+	INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
+	priv->sclass = gf110_disp_sclass;
 	priv->head.nr = heads;
 	priv->dac.nr = 3;
 	priv->sor.nr = 4;
 	priv->dac.power = nv50_dac_power;
 	priv->dac.sense = nv50_dac_sense;
 	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nvd0_hda_eld;
-	priv->sor.hdmi = nvd0_hdmi_ctrl;
+	priv->sor.hda_eld = gf110_hda_eld;
+	priv->sor.hdmi = gf110_hdmi_ctrl;
 	return 0;
 }
 
-struct nouveau_oclass *
-nvd0_disp_outp_sclass[] = {
-	&nvd0_sor_dp_impl.base.base,
+struct nvkm_oclass *
+gf110_disp_outp_sclass[] = {
+	&gf110_sor_dp_impl.base.base,
 	NULL
 };
 
-struct nouveau_oclass *
-nvd0_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+gf110_disp_oclass = &(struct nv50_disp_impl) {
 	.base.base.handle = NV_ENGINE(DISP, 0x90),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvd0_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
+		.ctor = gf110_disp_ctor,
+		.dtor = _nvkm_disp_dtor,
+		.init = _nvkm_disp_init,
+		.fini = _nvkm_disp_fini,
 	},
-	.base.vblank = &nvd0_disp_vblank_func,
-	.base.outp =  nvd0_disp_outp_sclass,
-	.mthd.core = &nvd0_disp_core_mthd_chan,
-	.mthd.base = &nvd0_disp_base_mthd_chan,
-	.mthd.ovly = &nvd0_disp_ovly_mthd_chan,
+	.base.vblank = &gf110_disp_vblank_func,
+	.base.outp =  gf110_disp_outp_sclass,
+	.mthd.core = &gf110_disp_core_mthd_chan,
+	.mthd.base = &gf110_disp_base_mthd_chan,
+	.mthd.ovly = &gf110_disp_ovly_mthd_chan,
 	.mthd.prev = -0x020000,
-	.head.scanoutpos = nvd0_disp_main_scanoutpos,
+	.head.scanoutpos = gf110_disp_main_scanoutpos,
 }.base.base;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nve0.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.c

@@ -21,20 +21,16 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
 
 #include <nvif/class.h>
 
-#include "nv50.h"
-
 /*******************************************************************************
  * EVO master channel object
  ******************************************************************************/
 
 static const struct nv50_disp_mthd_list
-nve0_disp_core_mthd_head = {
+gk104_disp_core_mthd_head = {
 	.mthd = 0x0300,
 	.addr = 0x000300,
 	.data = {
@@ -113,15 +109,15 @@ nve0_disp_core_mthd_head = {
 };
 
 const struct nv50_disp_mthd_chan
-nve0_disp_core_mthd_chan = {
+gk104_disp_core_mthd_chan = {
 	.name = "Core",
 	.addr = 0x000000,
 	.data = {
-		{ "Global", 1, &nvd0_disp_core_mthd_base },
-		{    "DAC", 3, &nvd0_disp_core_mthd_dac  },
-		{    "SOR", 8, &nvd0_disp_core_mthd_sor  },
-		{   "PIOR", 4, &nvd0_disp_core_mthd_pior },
-		{   "HEAD", 4, &nve0_disp_core_mthd_head },
+		{ "Global", 1, &gf110_disp_core_mthd_base },
+		{    "DAC", 3, &gf110_disp_core_mthd_dac  },
+		{    "SOR", 8, &gf110_disp_core_mthd_sor  },
+		{   "PIOR", 4, &gf110_disp_core_mthd_pior },
+		{   "HEAD", 4, &gk104_disp_core_mthd_head },
 		{}
 	}
 };
@@ -131,7 +127,7 @@ nve0_disp_core_mthd_chan = {
  ******************************************************************************/
 
 static const struct nv50_disp_mthd_list
-nve0_disp_ovly_mthd_base = {
+gk104_disp_ovly_mthd_base = {
 	.mthd = 0x0000,
 	.data = {
 		{ 0x0080, 0x665080 },
@@ -185,11 +181,11 @@ nve0_disp_ovly_mthd_base = {
 };
 
 const struct nv50_disp_mthd_chan
-nve0_disp_ovly_mthd_chan = {
+gk104_disp_ovly_mthd_chan = {
 	.name = "Overlay",
 	.addr = 0x001000,
 	.data = {
-		{ "Global", 1, &nve0_disp_ovly_mthd_base },
+		{ "Global", 1, &gk104_disp_ovly_mthd_base },
 		{}
 	}
 };
@@ -198,19 +194,19 @@ nve0_disp_ovly_mthd_chan = {
  * Base display object
  ******************************************************************************/
 
-static struct nouveau_oclass
-nve0_disp_sclass[] = {
-	{ GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
-	{ GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
-	{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
-	{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
-	{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
+static struct nvkm_oclass
+gk104_disp_sclass[] = {
+	{ GK104_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
+	{ GK104_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
+	{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
+	{ GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
+	{ GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
 	{}
 };
 
-static struct nouveau_oclass
-nve0_disp_main_oclass[] = {
-	{ GK104_DISP, &nvd0_disp_main_ofuncs },
+static struct nvkm_oclass
+gk104_disp_main_oclass[] = {
+	{ GK104_DISP, &gf110_disp_main_ofuncs },
 	{}
 };
 
@@ -219,54 +215,54 @@ nve0_disp_main_oclass[] = {
  ******************************************************************************/
 
 static int
-nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
+gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+		struct nvkm_oclass *oclass, void *data, u32 size,
+		struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv;
 	int heads = nv_rd32(parent, 0x022448);
 	int ret;
 
-	ret = nouveau_disp_create(parent, engine, oclass, heads,
-				  "PDISP", "display", &priv);
+	ret = nvkm_disp_create(parent, engine, oclass, heads,
+			       "PDISP", "display", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
-	ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+	ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
 	if (ret)
 		return ret;
 
-	nv_engine(priv)->sclass = nve0_disp_main_oclass;
+	nv_engine(priv)->sclass = gk104_disp_main_oclass;
 	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nvd0_disp_intr;
-	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
-	priv->sclass = nve0_disp_sclass;
+	nv_subdev(priv)->intr = gf110_disp_intr;
+	INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
+	priv->sclass = gk104_disp_sclass;
 	priv->head.nr = heads;
 	priv->dac.nr = 3;
 	priv->sor.nr = 4;
 	priv->dac.power = nv50_dac_power;
 	priv->dac.sense = nv50_dac_sense;
 	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nvd0_hda_eld;
-	priv->sor.hdmi = nve0_hdmi_ctrl;
+	priv->sor.hda_eld = gf110_hda_eld;
+	priv->sor.hdmi = gk104_hdmi_ctrl;
 	return 0;
 }
 
-struct nouveau_oclass *
-nve0_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+gk104_disp_oclass = &(struct nv50_disp_impl) {
 	.base.base.handle = NV_ENGINE(DISP, 0x91),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nve0_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
+		.ctor = gk104_disp_ctor,
+		.dtor = _nvkm_disp_dtor,
+		.init = _nvkm_disp_init,
+		.fini = _nvkm_disp_fini,
 	},
-	.base.vblank = &nvd0_disp_vblank_func,
-	.base.outp =  nvd0_disp_outp_sclass,
-	.mthd.core = &nve0_disp_core_mthd_chan,
-	.mthd.base = &nvd0_disp_base_mthd_chan,
-	.mthd.ovly = &nve0_disp_ovly_mthd_chan,
+	.base.vblank = &gf110_disp_vblank_func,
+	.base.outp =  gf110_disp_outp_sclass,
+	.mthd.core = &gk104_disp_core_mthd_chan,
+	.mthd.base = &gf110_disp_base_mthd_chan,
+	.mthd.ovly = &gk104_disp_ovly_mthd_chan,
 	.mthd.prev = -0x020000,
-	.head.scanoutpos = nvd0_disp_main_scanoutpos,
+	.head.scanoutpos = gf110_disp_main_scanoutpos,
 }.base.base;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nvf0.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.c

@@ -21,31 +21,27 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
 
 #include <nvif/class.h>
 
-#include "nv50.h"
-
 /*******************************************************************************
  * Base display object
  ******************************************************************************/
 
-static struct nouveau_oclass
-nvf0_disp_sclass[] = {
-	{ GK110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
-	{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
-	{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
-	{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
-	{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
+static struct nvkm_oclass
+gk110_disp_sclass[] = {
+	{ GK110_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
+	{ GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
+	{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
+	{ GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
+	{ GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
 	{}
 };
 
-static struct nouveau_oclass
-nvf0_disp_main_oclass[] = {
-	{ GK110_DISP, &nvd0_disp_main_ofuncs },
+static struct nvkm_oclass
+gk110_disp_main_oclass[] = {
+	{ GK110_DISP, &gf110_disp_main_ofuncs },
 	{}
 };
 
@@ -54,54 +50,54 @@ nvf0_disp_main_oclass[] = {
  ******************************************************************************/
 
 static int
-nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
+gk110_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+		struct nvkm_oclass *oclass, void *data, u32 size,
+		struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv;
 	int heads = nv_rd32(parent, 0x022448);
 	int ret;
 
-	ret = nouveau_disp_create(parent, engine, oclass, heads,
-				  "PDISP", "display", &priv);
+	ret = nvkm_disp_create(parent, engine, oclass, heads,
+			       "PDISP", "display", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
-	ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+	ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
 	if (ret)
 		return ret;
 
-	nv_engine(priv)->sclass = nvf0_disp_main_oclass;
+	nv_engine(priv)->sclass = gk110_disp_main_oclass;
 	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nvd0_disp_intr;
-	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
-	priv->sclass = nvf0_disp_sclass;
+	nv_subdev(priv)->intr = gf110_disp_intr;
+	INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
+	priv->sclass = gk110_disp_sclass;
 	priv->head.nr = heads;
 	priv->dac.nr = 3;
 	priv->sor.nr = 4;
 	priv->dac.power = nv50_dac_power;
 	priv->dac.sense = nv50_dac_sense;
 	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nvd0_hda_eld;
-	priv->sor.hdmi = nve0_hdmi_ctrl;
+	priv->sor.hda_eld = gf110_hda_eld;
+	priv->sor.hdmi = gk104_hdmi_ctrl;
 	return 0;
 }
 
-struct nouveau_oclass *
-nvf0_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+gk110_disp_oclass = &(struct nv50_disp_impl) {
 	.base.base.handle = NV_ENGINE(DISP, 0x92),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nvf0_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
+		.ctor = gk110_disp_ctor,
+		.dtor = _nvkm_disp_dtor,
+		.init = _nvkm_disp_init,
+		.fini = _nvkm_disp_fini,
 	},
-	.base.vblank = &nvd0_disp_vblank_func,
-	.base.outp =  nvd0_disp_outp_sclass,
-	.mthd.core = &nve0_disp_core_mthd_chan,
-	.mthd.base = &nvd0_disp_base_mthd_chan,
-	.mthd.ovly = &nve0_disp_ovly_mthd_chan,
+	.base.vblank = &gf110_disp_vblank_func,
+	.base.outp =  gf110_disp_outp_sclass,
+	.mthd.core = &gk104_disp_core_mthd_chan,
+	.mthd.base = &gf110_disp_base_mthd_chan,
+	.mthd.ovly = &gk104_disp_ovly_mthd_chan,
 	.mthd.prev = -0x020000,
-	.head.scanoutpos = nvd0_disp_main_scanoutpos,
+	.head.scanoutpos = gf110_disp_main_scanoutpos,
 }.base.base;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.c

@@ -21,31 +21,27 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
 
 #include <nvif/class.h>
 
-#include "nv50.h"
-
 /*******************************************************************************
  * Base display object
  ******************************************************************************/
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 gm107_disp_sclass[] = {
-	{ GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
-	{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
-	{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
-	{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
-	{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
+	{ GM107_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
+	{ GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
+	{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
+	{ GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
+	{ GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
 	{}
 };
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 gm107_disp_main_oclass[] = {
-	{ GM107_DISP, &nvd0_disp_main_ofuncs },
+	{ GM107_DISP, &gf110_disp_main_ofuncs },
 	{}
 };
 
@@ -54,28 +50,28 @@ gm107_disp_main_oclass[] = {
  ******************************************************************************/
 
 static int
-gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
+gm107_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+		struct nvkm_oclass *oclass, void *data, u32 size,
+		struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv;
 	int heads = nv_rd32(parent, 0x022448);
 	int ret;
 
-	ret = nouveau_disp_create(parent, engine, oclass, heads,
-				  "PDISP", "display", &priv);
+	ret = nvkm_disp_create(parent, engine, oclass, heads,
+			       "PDISP", "display", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
-	ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+	ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
 	if (ret)
 		return ret;
 
 	nv_engine(priv)->sclass = gm107_disp_main_oclass;
 	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nvd0_disp_intr;
-	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
+	nv_subdev(priv)->intr = gf110_disp_intr;
+	INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
 	priv->sclass = gm107_disp_sclass;
 	priv->head.nr = heads;
 	priv->dac.nr = 3;
@@ -83,25 +79,25 @@ gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	priv->dac.power = nv50_dac_power;
 	priv->dac.sense = nv50_dac_sense;
 	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nvd0_hda_eld;
-	priv->sor.hdmi = nve0_hdmi_ctrl;
+	priv->sor.hda_eld = gf110_hda_eld;
+	priv->sor.hdmi = gk104_hdmi_ctrl;
 	return 0;
 }
 
-struct nouveau_oclass *
+struct nvkm_oclass *
 gm107_disp_oclass = &(struct nv50_disp_impl) {
 	.base.base.handle = NV_ENGINE(DISP, 0x07),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = gm107_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
+		.dtor = _nvkm_disp_dtor,
+		.init = _nvkm_disp_init,
+		.fini = _nvkm_disp_fini,
 	},
-	.base.vblank = &nvd0_disp_vblank_func,
-	.base.outp =  nvd0_disp_outp_sclass,
-	.mthd.core = &nve0_disp_core_mthd_chan,
-	.mthd.base = &nvd0_disp_base_mthd_chan,
-	.mthd.ovly = &nve0_disp_ovly_mthd_chan,
+	.base.vblank = &gf110_disp_vblank_func,
+	.base.outp =  gf110_disp_outp_sclass,
+	.mthd.core = &gk104_disp_core_mthd_chan,
+	.mthd.base = &gf110_disp_base_mthd_chan,
+	.mthd.ovly = &gk104_disp_ovly_mthd_chan,
 	.mthd.prev = -0x020000,
-	.head.scanoutpos = nvd0_disp_main_scanoutpos,
+	.head.scanoutpos = gf110_disp_main_scanoutpos,
 }.base.base;

drivers/gpu/drm/nouveau/nvkm/engine/disp/gm204.c

@@ -21,31 +21,28 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
+#include "outpdp.h"
 
 #include <nvif/class.h>
 
-#include "nv50.h"
-
 /*******************************************************************************
  * Base display object
  ******************************************************************************/
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 gm204_disp_sclass[] = {
-	{ GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
-	{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
-	{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
-	{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
-	{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
+	{ GM204_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
+	{ GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
+	{ GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
+	{ GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
+	{ GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
 	{}
 };
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 gm204_disp_main_oclass[] = {
-	{ GM204_DISP, &nvd0_disp_main_ofuncs },
+	{ GM204_DISP, &gf110_disp_main_ofuncs },
 	{}
 };
 
@@ -54,28 +51,28 @@ gm204_disp_main_oclass[] = {
  ******************************************************************************/
 
 static int
-gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
+gm204_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+		struct nvkm_oclass *oclass, void *data, u32 size,
+		struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv;
 	int heads = nv_rd32(parent, 0x022448);
 	int ret;
 
-	ret = nouveau_disp_create(parent, engine, oclass, heads,
-				  "PDISP", "display", &priv);
+	ret = nvkm_disp_create(parent, engine, oclass, heads,
+			       "PDISP", "display", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
 
-	ret = nvkm_event_init(&nvd0_disp_chan_uevent, 1, 17, &priv->uevent);
+	ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent);
 	if (ret)
 		return ret;
 
 	nv_engine(priv)->sclass = gm204_disp_main_oclass;
 	nv_engine(priv)->cclass = &nv50_disp_cclass;
-	nv_subdev(priv)->intr = nvd0_disp_intr;
-	INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
+	nv_subdev(priv)->intr = gf110_disp_intr;
+	INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor);
 	priv->sclass = gm204_disp_sclass;
 	priv->head.nr = heads;
 	priv->dac.nr = 3;
@@ -83,32 +80,32 @@ gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	priv->dac.power = nv50_dac_power;
 	priv->dac.sense = nv50_dac_sense;
 	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nvd0_hda_eld;
-	priv->sor.hdmi = nvd0_hdmi_ctrl;
+	priv->sor.hda_eld = gf110_hda_eld;
+	priv->sor.hdmi = gf110_hdmi_ctrl;
 	priv->sor.magic = gm204_sor_magic;
 	return 0;
 }
 
-struct nouveau_oclass *
+struct nvkm_oclass *
 gm204_disp_outp_sclass[] = {
 	&gm204_sor_dp_impl.base.base,
 	NULL
 };
 
-struct nouveau_oclass *
+struct nvkm_oclass *
 gm204_disp_oclass = &(struct nv50_disp_impl) {
 	.base.base.handle = NV_ENGINE(DISP, 0x07),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = gm204_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
+		.dtor = _nvkm_disp_dtor,
+		.init = _nvkm_disp_init,
+		.fini = _nvkm_disp_fini,
 	},
-	.base.vblank = &nvd0_disp_vblank_func,
+	.base.vblank = &gf110_disp_vblank_func,
 	.base.outp =  gm204_disp_outp_sclass,
-	.mthd.core = &nve0_disp_core_mthd_chan,
-	.mthd.base = &nvd0_disp_base_mthd_chan,
-	.mthd.ovly = &nve0_disp_ovly_mthd_chan,
+	.mthd.core = &gk104_disp_core_mthd_chan,
+	.mthd.base = &gf110_disp_base_mthd_chan,
+	.mthd.ovly = &gk104_disp_ovly_mthd_chan,
 	.mthd.prev = -0x020000,
-	.head.scanoutpos = nvd0_disp_main_scanoutpos,
+	.head.scanoutpos = gf110_disp_main_scanoutpos,
 }.base.base;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nva0.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.c

@@ -21,20 +21,16 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
 
 #include <nvif/class.h>
 
-#include "nv50.h"
-
 /*******************************************************************************
  * EVO overlay channel objects
  ******************************************************************************/
 
 static const struct nv50_disp_mthd_list
-nva0_disp_ovly_mthd_base = {
+gt200_disp_ovly_mthd_base = {
 	.mthd = 0x0000,
 	.addr = 0x000000,
 	.data = {
@@ -65,11 +61,11 @@ nva0_disp_ovly_mthd_base = {
 };
 
 static const struct nv50_disp_mthd_chan
-nva0_disp_ovly_mthd_chan = {
+gt200_disp_ovly_mthd_chan = {
 	.name = "Overlay",
 	.addr = 0x000540,
 	.data = {
-		{ "Global", 1, &nva0_disp_ovly_mthd_base },
+		{ "Global", 1, &gt200_disp_ovly_mthd_base },
 		{}
 	}
 };
@@ -78,8 +74,8 @@ nva0_disp_ovly_mthd_chan = {
  * Base display object
  ******************************************************************************/
 
-static struct nouveau_oclass
-nva0_disp_sclass[] = {
+static struct nvkm_oclass
+gt200_disp_sclass[] = {
 	{ GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
 	{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
 	{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
@@ -88,8 +84,8 @@ nva0_disp_sclass[] = {
 	{}
 };
 
-static struct nouveau_oclass
-nva0_disp_main_oclass[] = {
+static struct nvkm_oclass
+gt200_disp_main_oclass[] = {
 	{ GT200_DISP, &nv50_disp_main_ofuncs },
 	{}
 };
@@ -99,15 +95,15 @@ nva0_disp_main_oclass[] = {
  ******************************************************************************/
 
 static int
-nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
+gt200_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+		struct nvkm_oclass *oclass, void *data, u32 size,
+		struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv;
 	int ret;
 
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
-				  "display", &priv);
+	ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
+			       "display", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -116,11 +112,11 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	if (ret)
 		return ret;
 
-	nv_engine(priv)->sclass = nva0_disp_main_oclass;
+	nv_engine(priv)->sclass = gt200_disp_main_oclass;
 	nv_engine(priv)->cclass = &nv50_disp_cclass;
 	nv_subdev(priv)->intr = nv50_disp_intr;
 	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
-	priv->sclass = nva0_disp_sclass;
+	priv->sclass = gt200_disp_sclass;
 	priv->head.nr = 2;
 	priv->dac.nr = 3;
 	priv->sor.nr = 2;
@@ -128,25 +124,25 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	priv->dac.power = nv50_dac_power;
 	priv->dac.sense = nv50_dac_sense;
 	priv->sor.power = nv50_sor_power;
-	priv->sor.hdmi = nv84_hdmi_ctrl;
+	priv->sor.hdmi = g84_hdmi_ctrl;
 	priv->pior.power = nv50_pior_power;
 	return 0;
 }
 
-struct nouveau_oclass *
-nva0_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+gt200_disp_oclass = &(struct nv50_disp_impl) {
 	.base.base.handle = NV_ENGINE(DISP, 0x83),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nva0_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
+		.ctor = gt200_disp_ctor,
+		.dtor = _nvkm_disp_dtor,
+		.init = _nvkm_disp_init,
+		.fini = _nvkm_disp_fini,
 	},
 	.base.vblank = &nv50_disp_vblank_func,
 	.base.outp =  nv50_disp_outp_sclass,
-	.mthd.core = &nv84_disp_core_mthd_chan,
-	.mthd.base = &nv84_disp_base_mthd_chan,
-	.mthd.ovly = &nva0_disp_ovly_mthd_chan,
+	.mthd.core = &g84_disp_core_mthd_chan,
+	.mthd.base = &g84_disp_base_mthd_chan,
+	.mthd.ovly = &gt200_disp_ovly_mthd_chan,
 	.mthd.prev = 0x000004,
 	.head.scanoutpos = nv50_disp_main_scanoutpos,
 }.base.base;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nva3.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.c

@@ -21,20 +21,16 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <engine/sw.h>
-#include <engine/disp.h>
+#include "nv50.h"
 
 #include <nvif/class.h>
 
-#include "nv50.h"
-
 /*******************************************************************************
  * Base display object
  ******************************************************************************/
 
-static struct nouveau_oclass
-nva3_disp_sclass[] = {
+static struct nvkm_oclass
+gt215_disp_sclass[] = {
 	{ GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
 	{ GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
 	{ GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
@@ -43,8 +39,8 @@ nva3_disp_sclass[] = {
 	{}
 };
 
-static struct nouveau_oclass
-nva3_disp_main_oclass[] = {
+static struct nvkm_oclass
+gt215_disp_main_oclass[] = {
 	{ GT214_DISP, &nv50_disp_main_ofuncs },
 	{}
 };
@@ -54,15 +50,15 @@ nva3_disp_main_oclass[] = {
  ******************************************************************************/
 
 static int
-nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
+gt215_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+		struct nvkm_oclass *oclass, void *data, u32 size,
+		struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv;
 	int ret;
 
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
-				  "display", &priv);
+	ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
+			       "display", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -71,11 +67,11 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	if (ret)
 		return ret;
 
-	nv_engine(priv)->sclass = nva3_disp_main_oclass;
+	nv_engine(priv)->sclass = gt215_disp_main_oclass;
 	nv_engine(priv)->cclass = &nv50_disp_cclass;
 	nv_subdev(priv)->intr = nv50_disp_intr;
 	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
-	priv->sclass = nva3_disp_sclass;
+	priv->sclass = gt215_disp_sclass;
 	priv->head.nr = 2;
 	priv->dac.nr = 3;
 	priv->sor.nr = 4;
@@ -83,26 +79,26 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	priv->dac.power = nv50_dac_power;
 	priv->dac.sense = nv50_dac_sense;
 	priv->sor.power = nv50_sor_power;
-	priv->sor.hda_eld = nva3_hda_eld;
-	priv->sor.hdmi = nva3_hdmi_ctrl;
+	priv->sor.hda_eld = gt215_hda_eld;
+	priv->sor.hdmi = gt215_hdmi_ctrl;
 	priv->pior.power = nv50_pior_power;
 	return 0;
 }
 
-struct nouveau_oclass *
-nva3_disp_oclass = &(struct nv50_disp_impl) {
+struct nvkm_oclass *
+gt215_disp_oclass = &(struct nv50_disp_impl) {
 	.base.base.handle = NV_ENGINE(DISP, 0x85),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
-		.ctor = nva3_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
+		.ctor = gt215_disp_ctor,
+		.dtor = _nvkm_disp_dtor,
+		.init = _nvkm_disp_init,
+		.fini = _nvkm_disp_fini,
 	},
 	.base.vblank = &nv50_disp_vblank_func,
-	.base.outp =  nv94_disp_outp_sclass,
-	.mthd.core = &nv94_disp_core_mthd_chan,
-	.mthd.base = &nv84_disp_base_mthd_chan,
-	.mthd.ovly = &nv84_disp_ovly_mthd_chan,
+	.base.outp =  g94_disp_outp_sclass,
+	.mthd.core = &g94_disp_core_mthd_chan,
+	.mthd.base = &g84_disp_base_mthd_chan,
+	.mthd.ovly = &g84_disp_ovly_mthd_chan,
 	.mthd.prev = 0x000004,
 	.head.scanoutpos = nv50_disp_main_scanoutpos,
 }.base.base;

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanvd0.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagf110.c

@@ -21,17 +21,19 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
+#include "outp.h"
 
 #include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
+#include <subdev/bios.h>
+#include <subdev/bios/dcb.h>
 #include <subdev/timer.h>
 
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
 
 int
-nvd0_hda_eld(NV50_DISP_MTHD_V1)
+gf110_hda_eld(NV50_DISP_MTHD_V1)
 {
 	union {
 		struct nv50_disp_sor_hda_eld_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdanva3.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/hdagt215.c

@@ -21,17 +21,17 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
+#include "outp.h"
 
 #include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
 #include <subdev/timer.h>
 
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
 
 int
-nva3_hda_eld(NV50_DISP_MTHD_V1)
+gt215_hda_eld(NV50_DISP_MTHD_V1)
 {
 	union {
 		struct nv50_disp_sor_hda_eld_v0 v0;

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminv84.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmig84.c

@@ -21,15 +21,15 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
 
 #include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
 
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
 
 int
-nv84_hdmi_ctrl(NV50_DISP_MTHD_V1)
+g84_hdmi_ctrl(NV50_DISP_MTHD_V1)
 {
 	const u32 hoff = (head * 0x800);
 	union {

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminvd0.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigf110.c

@@ -21,15 +21,15 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
 
 #include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
 
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
 
 int
-nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1)
+gf110_hdmi_ctrl(NV50_DISP_MTHD_V1)
 {
 	const u32 hoff = (head * 0x800);
 	union {

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminve0.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigk104.c

@@ -21,15 +21,15 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
 
 #include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
 
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
 
 int
-nve0_hdmi_ctrl(NV50_DISP_MTHD_V1)
+gk104_hdmi_ctrl(NV50_DISP_MTHD_V1)
 {
 	const u32 hoff = (head * 0x800);
 	const u32 hdmi = (head * 0x400);

drivers/gpu/drm/nouveau/nvkm/engine/disp/hdminva3.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmigt215.c

@@ -21,15 +21,16 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
+#include "outp.h"
 
 #include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
 
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
 
 int
-nva3_hdmi_ctrl(NV50_DISP_MTHD_V1)
+gt215_hdmi_ctrl(NV50_DISP_MTHD_V1)
 {
 	const u32 soff = outp->or * 0x800;
 	union {

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.c

@@ -21,20 +21,20 @@
  *
  * Authors: Ben Skeggs
  */
-
 #include "priv.h"
 
 #include <core/client.h>
-#include <core/event.h>
-#include <nvif/unpack.h>
+#include <core/device.h>
+
 #include <nvif/class.h>
+#include <nvif/unpack.h>
 
 struct nv04_disp_priv {
-	struct nouveau_disp base;
+	struct nvkm_disp base;
 };
 
 static int
-nv04_disp_scanoutpos(struct nouveau_object *object, struct nv04_disp_priv *priv,
+nv04_disp_scanoutpos(struct nvkm_object *object, struct nv04_disp_priv *priv,
 		     void *data, u32 size, int head)
 {
 	const u32 hoff = head * 0x2000;
@@ -75,7 +75,7 @@ nv04_disp_scanoutpos(struct nouveau_object *object, struct nv04_disp_priv *priv,
 }
 
 static int
-nv04_disp_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size)
+nv04_disp_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
 {
 	union {
 		struct nv04_disp_mthd_v0 v0;
@@ -105,17 +105,17 @@ nv04_disp_mthd(struct nouveau_object *object, u32 mthd, void *data, u32 size)
 	return -EINVAL;
 }
 
-static struct nouveau_ofuncs
+static struct nvkm_ofuncs
 nv04_disp_ofuncs = {
-	.ctor = _nouveau_object_ctor,
-	.dtor = nouveau_object_destroy,
-	.init = nouveau_object_init,
-	.fini = nouveau_object_fini,
+	.ctor = _nvkm_object_ctor,
+	.dtor = nvkm_object_destroy,
+	.init = nvkm_object_init,
+	.fini = nvkm_object_fini,
 	.mthd = nv04_disp_mthd,
-	.ntfy = nouveau_disp_ntfy,
+	.ntfy = nvkm_disp_ntfy,
 };
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 nv04_disp_sclass[] = {
 	{ NV04_DISP, &nv04_disp_ofuncs },
 	{},
@@ -128,26 +128,26 @@ nv04_disp_sclass[] = {
 static void
 nv04_disp_vblank_init(struct nvkm_event *event, int type, int head)
 {
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+	struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
 	nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000001);
 }
 
 static void
 nv04_disp_vblank_fini(struct nvkm_event *event, int type, int head)
 {
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+	struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
 	nv_wr32(disp, 0x600140 + (head * 0x2000) , 0x00000000);
 }
 
 static const struct nvkm_event_func
 nv04_disp_vblank_func = {
-	.ctor = nouveau_disp_vblank_ctor,
+	.ctor = nvkm_disp_vblank_ctor,
 	.init = nv04_disp_vblank_init,
 	.fini = nv04_disp_vblank_fini,
 };
 
 static void
-nv04_disp_intr(struct nouveau_subdev *subdev)
+nv04_disp_intr(struct nvkm_subdev *subdev)
 {
 	struct nv04_disp_priv *priv = (void *)subdev;
 	u32 crtc0 = nv_rd32(priv, 0x600100);
@@ -155,12 +155,12 @@ nv04_disp_intr(struct nouveau_subdev *subdev)
 	u32 pvideo;
 
 	if (crtc0 & 0x00000001) {
-		nouveau_disp_vblank(&priv->base, 0);
+		nvkm_disp_vblank(&priv->base, 0);
 		nv_wr32(priv, 0x600100, 0x00000001);
 	}
 
 	if (crtc1 & 0x00000001) {
-		nouveau_disp_vblank(&priv->base, 1);
+		nvkm_disp_vblank(&priv->base, 1);
 		nv_wr32(priv, 0x602100, 0x00000001);
 	}
 
@@ -174,15 +174,15 @@ nv04_disp_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nv04_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
+nv04_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+	       struct nvkm_oclass *oclass, void *data, u32 size,
+	       struct nvkm_object **pobject)
 {
 	struct nv04_disp_priv *priv;
 	int ret;
 
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "DISPLAY",
-				  "display", &priv);
+	ret = nvkm_disp_create(parent, engine, oclass, 2, "DISPLAY",
+			       "display", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -192,14 +192,14 @@ nv04_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	return 0;
 }
 
-struct nouveau_oclass *
-nv04_disp_oclass = &(struct nouveau_disp_impl) {
+struct nvkm_oclass *
+nv04_disp_oclass = &(struct nvkm_disp_impl) {
 	.base.handle = NV_ENGINE(DISP, 0x04),
-	.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv04_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
+		.dtor = _nvkm_disp_dtor,
+		.init = _nvkm_disp_init,
+		.fini = _nvkm_disp_fini,
 	},
 	.vblank = &nv04_disp_vblank_func,
 }.base;

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c

@@ -21,35 +21,38 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
+#include "outp.h"
+#include "outpdp.h"
 
-#include <core/object.h>
 #include <core/client.h>
-#include <core/parent.h>
-#include <core/handle.h>
+#include <core/device.h>
+#include <core/engctx.h>
 #include <core/enum.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-#include <nvif/event.h>
-
+#include <core/handle.h>
+#include <core/ramht.h>
+#include <engine/dmaobj.h>
 #include <subdev/bios.h>
 #include <subdev/bios/dcb.h>
 #include <subdev/bios/disp.h>
 #include <subdev/bios/init.h>
 #include <subdev/bios/pll.h>
 #include <subdev/devinit.h>
-#include <subdev/timer.h>
 #include <subdev/fb.h>
+#include <subdev/timer.h>
 
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/event.h>
+#include <nvif/unpack.h>
 
 /*******************************************************************************
  * EVO channel base class
  ******************************************************************************/
 
 static int
-nv50_disp_chan_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, int head,
+nv50_disp_chan_create_(struct nvkm_object *parent,
+		       struct nvkm_object *engine,
+		       struct nvkm_oclass *oclass, int head,
 		       int length, void **pobject)
 {
 	const struct nv50_disp_chan_impl *impl = (void *)oclass->ofuncs;
@@ -62,9 +65,9 @@ nv50_disp_chan_create_(struct nouveau_object *parent,
 		return -EBUSY;
 	base->chan |= (1 << chid);
 
-	ret = nouveau_namedb_create_(parent, engine, oclass, 0, NULL,
-				     (1ULL << NVDEV_ENGINE_DMAOBJ),
-				     length, pobject);
+	ret = nvkm_namedb_create_(parent, engine, oclass, 0, NULL,
+				  (1ULL << NVDEV_ENGINE_DMAOBJ),
+				  length, pobject);
 	chan = *pobject;
 	if (ret)
 		return ret;
@@ -80,7 +83,7 @@ nv50_disp_chan_destroy(struct nv50_disp_chan *chan)
 {
 	struct nv50_disp_base *base = (void *)nv_object(chan)->parent;
 	base->chan &= ~(1 << chan->chid);
-	nouveau_namedb_destroy(&chan->base);
+	nvkm_namedb_destroy(&chan->base);
 }
 
 static void
@@ -109,7 +112,7 @@ nv50_disp_chan_uevent_send(struct nv50_disp_priv *priv, int chid)
 }
 
 int
-nv50_disp_chan_uevent_ctor(struct nouveau_object *object, void *data, u32 size,
+nv50_disp_chan_uevent_ctor(struct nvkm_object *object, void *data, u32 size,
 			   struct nvkm_notify *notify)
 {
 	struct nv50_disp_dmac *dmac = (void *)object;
@@ -136,7 +139,7 @@ nv50_disp_chan_uevent = {
 };
 
 int
-nv50_disp_chan_ntfy(struct nouveau_object *object, u32 type,
+nv50_disp_chan_ntfy(struct nvkm_object *object, u32 type,
 		    struct nvkm_event **pevent)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
@@ -151,7 +154,7 @@ nv50_disp_chan_ntfy(struct nouveau_object *object, u32 type,
 }
 
 int
-nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size)
+nv50_disp_chan_map(struct nvkm_object *object, u64 *addr, u32 *size)
 {
 	struct nv50_disp_chan *chan = (void *)object;
 	*addr = nv_device_resource_start(nv_device(object), 0) +
@@ -161,7 +164,7 @@ nv50_disp_chan_map(struct nouveau_object *object, u64 *addr, u32 *size)
 }
 
 u32
-nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
+nv50_disp_chan_rd32(struct nvkm_object *object, u64 addr)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_chan *chan = (void *)object;
@@ -169,7 +172,7 @@ nv50_disp_chan_rd32(struct nouveau_object *object, u64 addr)
 }
 
 void
-nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data)
+nv50_disp_chan_wr32(struct nvkm_object *object, u64 addr, u32 data)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_chan *chan = (void *)object;
@@ -181,28 +184,28 @@ nv50_disp_chan_wr32(struct nouveau_object *object, u64 addr, u32 data)
  ******************************************************************************/
 
 static int
-nv50_disp_dmac_object_attach(struct nouveau_object *parent,
-			     struct nouveau_object *object, u32 name)
+nv50_disp_dmac_object_attach(struct nvkm_object *parent,
+			     struct nvkm_object *object, u32 name)
 {
 	struct nv50_disp_base *base = (void *)parent->parent;
 	struct nv50_disp_chan *chan = (void *)parent;
 	u32 addr = nv_gpuobj(object)->node->offset;
 	u32 chid = chan->chid;
 	u32 data = (chid << 28) | (addr << 10) | chid;
-	return nouveau_ramht_insert(base->ramht, chid, name, data);
+	return nvkm_ramht_insert(base->ramht, chid, name, data);
 }
 
 static void
-nv50_disp_dmac_object_detach(struct nouveau_object *parent, int cookie)
+nv50_disp_dmac_object_detach(struct nvkm_object *parent, int cookie)
 {
 	struct nv50_disp_base *base = (void *)parent->parent;
-	nouveau_ramht_remove(base->ramht, cookie);
+	nvkm_ramht_remove(base->ramht, cookie);
 }
 
 static int
-nv50_disp_dmac_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, u32 pushbuf, int head,
+nv50_disp_dmac_create_(struct nvkm_object *parent,
+		       struct nvkm_object *engine,
+		       struct nvkm_oclass *oclass, u32 pushbuf, int head,
 		       int length, void **pobject)
 {
 	struct nv50_disp_dmac *dmac;
@@ -214,7 +217,7 @@ nv50_disp_dmac_create_(struct nouveau_object *parent,
 	if (ret)
 		return ret;
 
-	dmac->pushdma = (void *)nouveau_handle_ref(parent, pushbuf);
+	dmac->pushdma = (void *)nvkm_handle_ref(parent, pushbuf);
 	if (!dmac->pushdma)
 		return -ENOENT;
 
@@ -243,15 +246,15 @@ nv50_disp_dmac_create_(struct nouveau_object *parent,
 }
 
 void
-nv50_disp_dmac_dtor(struct nouveau_object *object)
+nv50_disp_dmac_dtor(struct nvkm_object *object)
 {
 	struct nv50_disp_dmac *dmac = (void *)object;
-	nouveau_object_ref(NULL, (struct nouveau_object **)&dmac->pushdma);
+	nvkm_object_ref(NULL, (struct nvkm_object **)&dmac->pushdma);
 	nv50_disp_chan_destroy(&dmac->base);
 }
 
 static int
-nv50_disp_dmac_init(struct nouveau_object *object)
+nv50_disp_dmac_init(struct nvkm_object *object)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_dmac *dmac = (void *)object;
@@ -284,7 +287,7 @@ nv50_disp_dmac_init(struct nouveau_object *object)
 }
 
 static int
-nv50_disp_dmac_fini(struct nouveau_object *object, bool suspend)
+nv50_disp_dmac_fini(struct nvkm_object *object, bool suspend)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_dmac *dmac = (void *)object;
@@ -314,7 +317,7 @@ static void
 nv50_disp_mthd_list(struct nv50_disp_priv *priv, int debug, u32 base, int c,
 		    const struct nv50_disp_mthd_list *list, int inst)
 {
-	struct nouveau_object *disp = nv_object(priv);
+	struct nvkm_object *disp = nv_object(priv);
 	int i;
 
 	for (i = 0; list->data[i].mthd; i++) {
@@ -341,7 +344,7 @@ void
 nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head,
 		    const struct nv50_disp_mthd_chan *chan)
 {
-	struct nouveau_object *disp = nv_object(priv);
+	struct nvkm_object *disp = nv_object(priv);
 	const struct nv50_disp_impl *impl = (void *)disp->oclass;
 	const struct nv50_disp_mthd_list *list;
 	int i, j;
@@ -482,10 +485,10 @@ nv50_disp_core_mthd_chan = {
 };
 
 int
-nv50_disp_core_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
+nv50_disp_core_ctor(struct nvkm_object *parent,
+		    struct nvkm_object *engine,
+		    struct nvkm_oclass *oclass, void *data, u32 size,
+		    struct nvkm_object **pobject)
 {
 	union {
 		struct nv50_disp_core_channel_dma_v0 v0;
@@ -511,7 +514,7 @@ nv50_disp_core_ctor(struct nouveau_object *parent,
 }
 
 static int
-nv50_disp_core_init(struct nouveau_object *object)
+nv50_disp_core_init(struct nvkm_object *object)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_dmac *mast = (void *)object;
@@ -548,7 +551,7 @@ nv50_disp_core_init(struct nouveau_object *object)
 }
 
 static int
-nv50_disp_core_fini(struct nouveau_object *object, bool suspend)
+nv50_disp_core_fini(struct nvkm_object *object, bool suspend)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_dmac *mast = (void *)object;
@@ -638,10 +641,10 @@ nv50_disp_base_mthd_chan = {
 };
 
 int
-nv50_disp_base_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
+nv50_disp_base_ctor(struct nvkm_object *parent,
+		    struct nvkm_object *engine,
+		    struct nvkm_oclass *oclass, void *data, u32 size,
+		    struct nvkm_object **pobject)
 {
 	union {
 		struct nv50_disp_base_channel_dma_v0 v0;
@@ -728,10 +731,10 @@ nv50_disp_ovly_mthd_chan = {
 };
 
 int
-nv50_disp_ovly_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
+nv50_disp_ovly_ctor(struct nvkm_object *parent,
+		    struct nvkm_object *engine,
+		    struct nvkm_oclass *oclass, void *data, u32 size,
+		    struct nvkm_object **pobject)
 {
 	union {
 		struct nv50_disp_overlay_channel_dma_v0 v0;
@@ -780,9 +783,9 @@ nv50_disp_ovly_ofuncs = {
  ******************************************************************************/
 
 static int
-nv50_disp_pioc_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass, int head,
+nv50_disp_pioc_create_(struct nvkm_object *parent,
+		       struct nvkm_object *engine,
+		       struct nvkm_oclass *oclass, int head,
 		       int length, void **pobject)
 {
 	return nv50_disp_chan_create_(parent, engine, oclass, head,
@@ -790,14 +793,14 @@ nv50_disp_pioc_create_(struct nouveau_object *parent,
 }
 
 void
-nv50_disp_pioc_dtor(struct nouveau_object *object)
+nv50_disp_pioc_dtor(struct nvkm_object *object)
 {
 	struct nv50_disp_pioc *pioc = (void *)object;
 	nv50_disp_chan_destroy(&pioc->base);
 }
 
 static int
-nv50_disp_pioc_init(struct nouveau_object *object)
+nv50_disp_pioc_init(struct nvkm_object *object)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_pioc *pioc = (void *)object;
@@ -826,7 +829,7 @@ nv50_disp_pioc_init(struct nouveau_object *object)
 }
 
 static int
-nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend)
+nv50_disp_pioc_fini(struct nvkm_object *object, bool suspend)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_pioc *pioc = (void *)object;
@@ -848,10 +851,10 @@ nv50_disp_pioc_fini(struct nouveau_object *object, bool suspend)
  ******************************************************************************/
 
 int
-nv50_disp_oimm_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
+nv50_disp_oimm_ctor(struct nvkm_object *parent,
+		    struct nvkm_object *engine,
+		    struct nvkm_oclass *oclass, void *data, u32 size,
+		    struct nvkm_object **pobject)
 {
 	union {
 		struct nv50_disp_overlay_v0 v0;
@@ -896,10 +899,10 @@ nv50_disp_oimm_ofuncs = {
  ******************************************************************************/
 
 int
-nv50_disp_curs_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
+nv50_disp_curs_ctor(struct nvkm_object *parent,
+		    struct nvkm_object *engine,
+		    struct nvkm_oclass *oclass, void *data, u32 size,
+		    struct nvkm_object **pobject)
 {
 	union {
 		struct nv50_disp_cursor_v0 v0;
@@ -976,8 +979,7 @@ nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
 }
 
 int
-nv50_disp_main_mthd(struct nouveau_object *object, u32 mthd,
-		    void *data, u32 size)
+nv50_disp_main_mthd(struct nvkm_object *object, u32 mthd, void *data, u32 size)
 {
 	const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine);
 	union {
@@ -1100,42 +1102,42 @@ nv50_disp_main_mthd(struct nouveau_object *object, u32 mthd,
 }
 
 int
-nv50_disp_main_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
+nv50_disp_main_ctor(struct nvkm_object *parent,
+		    struct nvkm_object *engine,
+		    struct nvkm_oclass *oclass, void *data, u32 size,
+		    struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv = (void *)engine;
 	struct nv50_disp_base *base;
 	int ret;
 
-	ret = nouveau_parent_create(parent, engine, oclass, 0,
-				    priv->sclass, 0, &base);
+	ret = nvkm_parent_create(parent, engine, oclass, 0,
+				 priv->sclass, 0, &base);
 	*pobject = nv_object(base);
 	if (ret)
 		return ret;
 
-	return nouveau_ramht_new(nv_object(base), nv_object(base), 0x1000, 0,
-				&base->ramht);
+	return nvkm_ramht_new(nv_object(base), nv_object(base), 0x1000, 0,
+			      &base->ramht);
 }
 
 void
-nv50_disp_main_dtor(struct nouveau_object *object)
+nv50_disp_main_dtor(struct nvkm_object *object)
 {
 	struct nv50_disp_base *base = (void *)object;
-	nouveau_ramht_ref(NULL, &base->ramht);
-	nouveau_parent_destroy(&base->base);
+	nvkm_ramht_ref(NULL, &base->ramht);
+	nvkm_parent_destroy(&base->base);
 }
 
 static int
-nv50_disp_main_init(struct nouveau_object *object)
+nv50_disp_main_init(struct nvkm_object *object)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_base *base = (void *)object;
 	int ret, i;
 	u32 tmp;
 
-	ret = nouveau_parent_init(&base->base);
+	ret = nvkm_parent_init(&base->base);
 	if (ret)
 		return ret;
 
@@ -1196,7 +1198,7 @@ nv50_disp_main_init(struct nouveau_object *object)
 }
 
 static int
-nv50_disp_main_fini(struct nouveau_object *object, bool suspend)
+nv50_disp_main_fini(struct nvkm_object *object, bool suspend)
 {
 	struct nv50_disp_priv *priv = (void *)object->engine;
 	struct nv50_disp_base *base = (void *)object;
@@ -1205,26 +1207,26 @@ nv50_disp_main_fini(struct nouveau_object *object, bool suspend)
 	nv_wr32(priv, 0x610024, 0x00000000);
 	nv_wr32(priv, 0x610020, 0x00000000);
 
-	return nouveau_parent_fini(&base->base, suspend);
+	return nvkm_parent_fini(&base->base, suspend);
 }
 
-struct nouveau_ofuncs
+struct nvkm_ofuncs
 nv50_disp_main_ofuncs = {
 	.ctor = nv50_disp_main_ctor,
 	.dtor = nv50_disp_main_dtor,
 	.init = nv50_disp_main_init,
 	.fini = nv50_disp_main_fini,
 	.mthd = nv50_disp_main_mthd,
-	.ntfy = nouveau_disp_ntfy,
+	.ntfy = nvkm_disp_ntfy,
 };
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 nv50_disp_main_oclass[] = {
 	{ NV50_DISP, &nv50_disp_main_ofuncs },
 	{}
 };
 
-static struct nouveau_oclass
+static struct nvkm_oclass
 nv50_disp_sclass[] = {
 	{ NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
 	{ NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
@@ -1240,13 +1242,13 @@ nv50_disp_sclass[] = {
  ******************************************************************************/
 
 static int
-nv50_disp_data_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *data, u32 size,
-		    struct nouveau_object **pobject)
+nv50_disp_data_ctor(struct nvkm_object *parent,
+		    struct nvkm_object *engine,
+		    struct nvkm_oclass *oclass, void *data, u32 size,
+		    struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv = (void *)engine;
-	struct nouveau_engctx *ectx;
+	struct nvkm_engctx *ectx;
 	int ret = -EBUSY;
 
 	/* no context needed for channel objects... */
@@ -1259,25 +1261,24 @@ nv50_disp_data_ctor(struct nouveau_object *parent,
 	/* allocate display hardware to client */
 	mutex_lock(&nv_subdev(priv)->mutex);
 	if (list_empty(&nv_engine(priv)->contexts)) {
-		ret = nouveau_engctx_create(parent, engine, oclass, NULL,
-					    0x10000, 0x10000,
-					    NVOBJ_FLAG_HEAP, &ectx);
+		ret = nvkm_engctx_create(parent, engine, oclass, NULL, 0x10000,
+					 0x10000, NVOBJ_FLAG_HEAP, &ectx);
 		*pobject = nv_object(ectx);
 	}
 	mutex_unlock(&nv_subdev(priv)->mutex);
 	return ret;
 }
 
-struct nouveau_oclass
+struct nvkm_oclass
 nv50_disp_cclass = {
 	.handle = NV_ENGCTX(DISP, 0x50),
-	.ofuncs = &(struct nouveau_ofuncs) {
+	.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv50_disp_data_ctor,
-		.dtor = _nouveau_engctx_dtor,
-		.init = _nouveau_engctx_init,
-		.fini = _nouveau_engctx_fini,
-		.rd32 = _nouveau_engctx_rd32,
-		.wr32 = _nouveau_engctx_wr32,
+		.dtor = _nvkm_engctx_dtor,
+		.init = _nvkm_engctx_init,
+		.fini = _nvkm_engctx_fini,
+		.rd32 = _nvkm_engctx_rd32,
+		.wr32 = _nvkm_engctx_wr32,
 	},
 };
 
@@ -1288,25 +1289,25 @@ nv50_disp_cclass = {
 static void
 nv50_disp_vblank_fini(struct nvkm_event *event, int type, int head)
 {
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+	struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
 	nv_mask(disp, 0x61002c, (4 << head), 0);
 }
 
 static void
 nv50_disp_vblank_init(struct nvkm_event *event, int type, int head)
 {
-	struct nouveau_disp *disp = container_of(event, typeof(*disp), vblank);
+	struct nvkm_disp *disp = container_of(event, typeof(*disp), vblank);
 	nv_mask(disp, 0x61002c, (4 << head), (4 << head));
 }
 
 const struct nvkm_event_func
 nv50_disp_vblank_func = {
-	.ctor = nouveau_disp_vblank_ctor,
+	.ctor = nvkm_disp_vblank_ctor,
 	.init = nv50_disp_vblank_init,
 	.fini = nv50_disp_vblank_fini,
 };
 
-static const struct nouveau_enum
+static const struct nvkm_enum
 nv50_disp_intr_error_type[] = {
 	{ 3, "ILLEGAL_MTHD" },
 	{ 4, "INVALID_VALUE" },
@@ -1315,7 +1316,7 @@ nv50_disp_intr_error_type[] = {
 	{}
 };
 
-static const struct nouveau_enum
+static const struct nvkm_enum
 nv50_disp_intr_error_code[] = {
 	{ 0x00, "" },
 	{}
@@ -1330,14 +1331,14 @@ nv50_disp_intr_error(struct nv50_disp_priv *priv, int chid)
 	u32 code = (addr & 0x00ff0000) >> 16;
 	u32 type = (addr & 0x00007000) >> 12;
 	u32 mthd = (addr & 0x00000ffc);
-	const struct nouveau_enum *ec, *et;
+	const struct nvkm_enum *ec, *et;
 	char ecunk[6], etunk[6];
 
-	et = nouveau_enum_find(nv50_disp_intr_error_type, type);
+	et = nvkm_enum_find(nv50_disp_intr_error_type, type);
 	if (!et)
 		snprintf(etunk, sizeof(etunk), "UNK%02X", type);
 
-	ec = nouveau_enum_find(nv50_disp_intr_error_code, code);
+	ec = nvkm_enum_find(nv50_disp_intr_error_code, code);
 	if (!ec)
 		snprintf(ecunk, sizeof(ecunk), "UNK%02X", code);
 
@@ -1385,7 +1386,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl,
 	    u32 *data, u8 *ver, u8 *hdr, u8 *cnt, u8 *len,
 	    struct nvbios_outp *info)
 {
-	struct nouveau_bios *bios = nouveau_bios(priv);
+	struct nvkm_bios *bios = nvkm_bios(priv);
 	struct nvkm_output *outp;
 	u16 mask, type;
 
@@ -1440,7 +1441,7 @@ exec_lookup(struct nv50_disp_priv *priv, int head, int or, u32 ctrl,
 static struct nvkm_output *
 exec_script(struct nv50_disp_priv *priv, int head, int id)
 {
-	struct nouveau_bios *bios = nouveau_bios(priv);
+	struct nvkm_bios *bios = nvkm_bios(priv);
 	struct nvkm_output *outp;
 	struct nvbios_outp info;
 	u8  ver, hdr, cnt, len;
@@ -1497,7 +1498,7 @@ exec_script(struct nv50_disp_priv *priv, int head, int id)
 static struct nvkm_output *
 exec_clkcmp(struct nv50_disp_priv *priv, int head, int id, u32 pclk, u32 *conf)
 {
-	struct nouveau_bios *bios = nouveau_bios(priv);
+	struct nvkm_bios *bios = nvkm_bios(priv);
 	struct nvkm_output *outp;
 	struct nvbios_outp info1;
 	struct nvbios_ocfg info2;
@@ -1610,7 +1611,7 @@ nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head)
 		struct nvkm_output_dp *outpdp = (void *)outp;
 		struct nvbios_init init = {
 			.subdev = nv_subdev(priv),
-			.bios = nouveau_bios(priv),
+			.bios = nvkm_bios(priv),
 			.outp = &outp->info,
 			.crtc = head,
 			.offset = outpdp->info.script[4],
@@ -1625,7 +1626,7 @@ nv50_disp_intr_unk20_0(struct nv50_disp_priv *priv, int head)
 static void
 nv50_disp_intr_unk20_1(struct nv50_disp_priv *priv, int head)
 {
-	struct nouveau_devinit *devinit = nouveau_devinit(priv);
+	struct nvkm_devinit *devinit = nvkm_devinit(priv);
 	u32 pclk = nv_rd32(priv, 0x610ad0 + (head * 0x540)) & 0x3fffff;
 	if (pclk)
 		devinit->pll_set(devinit, PLL_VPLL0 + head, pclk);
@@ -1841,9 +1842,10 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
  * programmed for DisplayPort.
  */
 static void
-nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv, struct dcb_output *outp)
+nv50_disp_intr_unk40_0_tmds(struct nv50_disp_priv *priv,
+			    struct dcb_output *outp)
 {
-	struct nouveau_bios *bios = nouveau_bios(priv);
+	struct nvkm_bios *bios = nvkm_bios(priv);
 	const int link = !(outp->sorconf.link & 1);
 	const int   or = ffs(outp->or) - 1;
 	const u32 loff = (or * 0x800) + (link * 0x80);
@@ -1920,7 +1922,7 @@ nv50_disp_intr_supervisor(struct work_struct *work)
 }
 
 void
-nv50_disp_intr(struct nouveau_subdev *subdev)
+nv50_disp_intr(struct nvkm_subdev *subdev)
 {
 	struct nv50_disp_priv *priv = (void *)subdev;
 	u32 intr0 = nv_rd32(priv, 0x610020);
@@ -1939,13 +1941,13 @@ nv50_disp_intr(struct nouveau_subdev *subdev)
 	}
 
 	if (intr1 & 0x00000004) {
-		nouveau_disp_vblank(&priv->base, 0);
+		nvkm_disp_vblank(&priv->base, 0);
 		nv_wr32(priv, 0x610024, 0x00000004);
 		intr1 &= ~0x00000004;
 	}
 
 	if (intr1 & 0x00000008) {
-		nouveau_disp_vblank(&priv->base, 1);
+		nvkm_disp_vblank(&priv->base, 1);
 		nv_wr32(priv, 0x610024, 0x00000008);
 		intr1 &= ~0x00000008;
 	}
@@ -1959,15 +1961,15 @@ nv50_disp_intr(struct nouveau_subdev *subdev)
 }
 
 static int
-nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-	       struct nouveau_oclass *oclass, void *data, u32 size,
-	       struct nouveau_object **pobject)
+nv50_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
+	       struct nvkm_oclass *oclass, void *data, u32 size,
+	       struct nvkm_object **pobject)
 {
 	struct nv50_disp_priv *priv;
 	int ret;
 
-	ret = nouveau_disp_create(parent, engine, oclass, 2, "PDISP",
-				  "display", &priv);
+	ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
+			       "display", &priv);
 	*pobject = nv_object(priv);
 	if (ret)
 		return ret;
@@ -1992,20 +1994,20 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
 	return 0;
 }
 
-struct nouveau_oclass *
+struct nvkm_oclass *
 nv50_disp_outp_sclass[] = {
 	&nv50_pior_dp_impl.base.base,
 	NULL
 };
 
-struct nouveau_oclass *
+struct nvkm_oclass *
 nv50_disp_oclass = &(struct nv50_disp_impl) {
 	.base.base.handle = NV_ENGINE(DISP, 0x50),
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv50_disp_ctor,
-		.dtor = _nouveau_disp_dtor,
-		.init = _nouveau_disp_init,
-		.fini = _nouveau_disp_fini,
+		.dtor = _nvkm_disp_dtor,
+		.init = _nvkm_disp_init,
+		.fini = _nvkm_disp_fini,
 	},
 	.base.vblank = &nv50_disp_vblank_func,
 	.base.outp =  nv50_disp_outp_sclass,

drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h

@@ -1,27 +1,17 @@
 #ifndef __NV50_DISP_H__
 #define __NV50_DISP_H__
-
-#include <core/parent.h>
-#include <core/namedb.h>
-#include <core/engctx.h>
-#include <core/ramht.h>
-#include <core/event.h>
-
-#include <engine/dmaobj.h>
-
-#include "dport.h"
 #include "priv.h"
-#include "outp.h"
-#include "outpdp.h"
+struct nvkm_output;
+struct nvkm_output_dp;
 
-#define NV50_DISP_MTHD_ struct nouveau_object *object,                         \
+#define NV50_DISP_MTHD_ struct nvkm_object *object,                            \
 	struct nv50_disp_priv *priv, void *data, u32 size
 #define NV50_DISP_MTHD_V0 NV50_DISP_MTHD_, int head
 #define NV50_DISP_MTHD_V1 NV50_DISP_MTHD_, int head, struct nvkm_output *outp
 
 struct nv50_disp_priv {
-	struct nouveau_disp base;
-	struct nouveau_oclass *sclass;
+	struct nvkm_disp base;
+	struct nvkm_oclass *sclass;
 
 	struct work_struct supervisor;
 	u32 super;
@@ -52,7 +42,7 @@ struct nv50_disp_priv {
 };
 
 struct nv50_disp_impl {
-	struct nouveau_disp_impl base;
+	struct nvkm_disp_impl base;
 	struct {
 		const struct nv50_disp_mthd_chan *core;
 		const struct nv50_disp_mthd_chan *base;
@@ -65,90 +55,75 @@ struct nv50_disp_impl {
 };
 
 int nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
-int nv50_disp_main_mthd(struct nouveau_object *, u32, void *, u32);
+int nv50_disp_main_mthd(struct nvkm_object *, u32, void *, u32);
 
-int nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
+int gf110_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
 
 int nv50_dac_power(NV50_DISP_MTHD_V1);
 int nv50_dac_sense(NV50_DISP_MTHD_V1);
 
-int nva3_hda_eld(NV50_DISP_MTHD_V1);
-int nvd0_hda_eld(NV50_DISP_MTHD_V1);
+int gt215_hda_eld(NV50_DISP_MTHD_V1);
+int gf110_hda_eld(NV50_DISP_MTHD_V1);
 
-int nv84_hdmi_ctrl(NV50_DISP_MTHD_V1);
-int nva3_hdmi_ctrl(NV50_DISP_MTHD_V1);
-int nvd0_hdmi_ctrl(NV50_DISP_MTHD_V1);
-int nve0_hdmi_ctrl(NV50_DISP_MTHD_V1);
+int g84_hdmi_ctrl(NV50_DISP_MTHD_V1);
+int gt215_hdmi_ctrl(NV50_DISP_MTHD_V1);
+int gf110_hdmi_ctrl(NV50_DISP_MTHD_V1);
+int gk104_hdmi_ctrl(NV50_DISP_MTHD_V1);
 
 int nv50_sor_power(NV50_DISP_MTHD_V1);
-
-int nv94_sor_dp_train_init(struct nv50_disp_priv *, int, int, int, u16, u16,
-		           u32, struct dcb_output *);
-int nv94_sor_dp_train_fini(struct nv50_disp_priv *, int, int, int, u16, u16,
-		           u32, struct dcb_output *);
-int nv94_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32,
-		      struct dcb_output *);
-int nv94_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
-		       struct dcb_output *);
-int nv94_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
-		       struct dcb_output *);
-
-int nvd0_sor_dp_train(struct nv50_disp_priv *, int, int, u16, u16, u32,
-		      struct dcb_output *);
-int nvd0_sor_dp_lnkctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
-		       struct dcb_output *);
-int nvd0_sor_dp_drvctl(struct nv50_disp_priv *, int, int, int, u16, u16, u32,
-		       struct dcb_output *);
-
 int nv50_pior_power(NV50_DISP_MTHD_V1);
 
+#include <core/parent.h>
+
 struct nv50_disp_base {
-	struct nouveau_parent base;
-	struct nouveau_ramht *ramht;
+	struct nvkm_parent base;
+	struct nvkm_ramht *ramht;
 	u32 chan;
 };
 
 struct nv50_disp_chan_impl {
-	struct nouveau_ofuncs base;
+	struct nvkm_ofuncs base;
 	int chid;
-	int  (*attach)(struct nouveau_object *, struct nouveau_object *, u32);
-	void (*detach)(struct nouveau_object *, int);
+	int  (*attach)(struct nvkm_object *, struct nvkm_object *, u32);
+	void (*detach)(struct nvkm_object *, int);
 };
 
+#include <core/namedb.h>
+
 struct nv50_disp_chan {
-	struct nouveau_namedb base;
+	struct nvkm_namedb base;
 	int chid;
 };
 
-int  nv50_disp_chan_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
-int  nv50_disp_chan_map(struct nouveau_object *, u64 *, u32 *);
-u32  nv50_disp_chan_rd32(struct nouveau_object *, u64);
-void nv50_disp_chan_wr32(struct nouveau_object *, u64, u32);
+int  nv50_disp_chan_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
+int  nv50_disp_chan_map(struct nvkm_object *, u64 *, u32 *);
+u32  nv50_disp_chan_rd32(struct nvkm_object *, u64);
+void nv50_disp_chan_wr32(struct nvkm_object *, u64, u32);
 extern const struct nvkm_event_func nv50_disp_chan_uevent;
-int  nv50_disp_chan_uevent_ctor(struct nouveau_object *, void *, u32,
+int  nv50_disp_chan_uevent_ctor(struct nvkm_object *, void *, u32,
 				struct nvkm_notify *);
 void nv50_disp_chan_uevent_send(struct nv50_disp_priv *, int);
 
-extern const struct nvkm_event_func nvd0_disp_chan_uevent;
+extern const struct nvkm_event_func gf110_disp_chan_uevent;
 
 #define nv50_disp_chan_init(a)                                                 \
-	nouveau_namedb_init(&(a)->base)
+	nvkm_namedb_init(&(a)->base)
 #define nv50_disp_chan_fini(a,b)                                               \
-	nouveau_namedb_fini(&(a)->base, (b))
+	nvkm_namedb_fini(&(a)->base, (b))
 
 struct nv50_disp_dmac {
 	struct nv50_disp_chan base;
-	struct nouveau_dmaobj *pushdma;
+	struct nvkm_dmaobj *pushdma;
 	u32 push;
 };
 
-void nv50_disp_dmac_dtor(struct nouveau_object *);
+void nv50_disp_dmac_dtor(struct nvkm_object *);
 
 struct nv50_disp_pioc {
 	struct nv50_disp_chan base;
 };
 
-void nv50_disp_pioc_dtor(struct nouveau_object *);
+void nv50_disp_pioc_dtor(struct nvkm_object *);
 
 struct nv50_disp_mthd_list {
 	u32 mthd;
@@ -171,82 +146,81 @@ struct nv50_disp_mthd_chan {
 };
 
 extern struct nv50_disp_chan_impl nv50_disp_core_ofuncs;
-int nv50_disp_core_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
+int nv50_disp_core_ctor(struct nvkm_object *, struct nvkm_object *,
+			struct nvkm_oclass *, void *, u32,
+			struct nvkm_object **);
 extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_base;
 extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_sor;
 extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_pior;
 extern struct nv50_disp_chan_impl nv50_disp_base_ofuncs;
-int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
+int nv50_disp_base_ctor(struct nvkm_object *, struct nvkm_object *,
+			struct nvkm_oclass *, void *, u32,
+			struct nvkm_object **);
 extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image;
 extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs;
-int nv50_disp_ovly_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
+int nv50_disp_ovly_ctor(struct nvkm_object *, struct nvkm_object *,
+			struct nvkm_oclass *, void *, u32,
+			struct nvkm_object **);
 extern const struct nv50_disp_mthd_list nv50_disp_ovly_mthd_base;
 extern struct nv50_disp_chan_impl nv50_disp_oimm_ofuncs;
-int nv50_disp_oimm_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
+int nv50_disp_oimm_ctor(struct nvkm_object *, struct nvkm_object *,
+			struct nvkm_oclass *, void *, u32,
+			struct nvkm_object **);
 extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs;
-int nv50_disp_curs_ctor(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, void *, u32,
-			struct nouveau_object **);
-extern struct nouveau_ofuncs nv50_disp_main_ofuncs;
-int  nv50_disp_main_ctor(struct nouveau_object *, struct nouveau_object *,
-			 struct nouveau_oclass *, void *, u32,
-			 struct nouveau_object **);
-void nv50_disp_main_dtor(struct nouveau_object *);
-extern struct nouveau_omthds nv50_disp_main_omthds[];
-extern struct nouveau_oclass nv50_disp_cclass;
+int nv50_disp_curs_ctor(struct nvkm_object *, struct nvkm_object *,
+			struct nvkm_oclass *, void *, u32,
+			struct nvkm_object **);
+extern struct nvkm_ofuncs nv50_disp_main_ofuncs;
+int  nv50_disp_main_ctor(struct nvkm_object *, struct nvkm_object *,
+			 struct nvkm_oclass *, void *, u32,
+			 struct nvkm_object **);
+void nv50_disp_main_dtor(struct nvkm_object *);
+extern struct nvkm_omthds nv50_disp_main_omthds[];
+extern struct nvkm_oclass nv50_disp_cclass;
 void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head,
 			 const struct nv50_disp_mthd_chan *);
 void nv50_disp_intr_supervisor(struct work_struct *);
-void nv50_disp_intr(struct nouveau_subdev *);
+void nv50_disp_intr(struct nvkm_subdev *);
 extern const struct nvkm_event_func nv50_disp_vblank_func;
 
-extern const struct nv50_disp_mthd_chan nv84_disp_core_mthd_chan;
-extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_dac;
-extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_head;
-extern const struct nv50_disp_mthd_chan nv84_disp_base_mthd_chan;
-extern const struct nv50_disp_mthd_chan nv84_disp_ovly_mthd_chan;
-
-extern const struct nv50_disp_mthd_chan nv94_disp_core_mthd_chan;
-
-extern struct nv50_disp_chan_impl nvd0_disp_core_ofuncs;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_base;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_dac;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_sor;
-extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_pior;
-extern struct nv50_disp_chan_impl nvd0_disp_base_ofuncs;
-extern struct nv50_disp_chan_impl nvd0_disp_ovly_ofuncs;
-extern const struct nv50_disp_mthd_chan nvd0_disp_base_mthd_chan;
-extern struct nv50_disp_chan_impl nvd0_disp_oimm_ofuncs;
-extern struct nv50_disp_chan_impl nvd0_disp_curs_ofuncs;
-extern struct nouveau_ofuncs nvd0_disp_main_ofuncs;
-extern struct nouveau_oclass nvd0_disp_cclass;
-void nvd0_disp_intr_supervisor(struct work_struct *);
-void nvd0_disp_intr(struct nouveau_subdev *);
-extern const struct nvkm_event_func nvd0_disp_vblank_func;
-
-extern const struct nv50_disp_mthd_chan nve0_disp_core_mthd_chan;
-extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan;
+extern const struct nv50_disp_mthd_chan g84_disp_core_mthd_chan;
+extern const struct nv50_disp_mthd_list g84_disp_core_mthd_dac;
+extern const struct nv50_disp_mthd_list g84_disp_core_mthd_head;
+extern const struct nv50_disp_mthd_chan g84_disp_base_mthd_chan;
+extern const struct nv50_disp_mthd_chan g84_disp_ovly_mthd_chan;
+
+extern const struct nv50_disp_mthd_chan g94_disp_core_mthd_chan;
+
+extern struct nv50_disp_chan_impl gf110_disp_core_ofuncs;
+extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_base;
+extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_dac;
+extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_sor;
+extern const struct nv50_disp_mthd_list gf110_disp_core_mthd_pior;
+extern struct nv50_disp_chan_impl gf110_disp_base_ofuncs;
+extern struct nv50_disp_chan_impl gf110_disp_ovly_ofuncs;
+extern const struct nv50_disp_mthd_chan gf110_disp_base_mthd_chan;
+extern struct nv50_disp_chan_impl gf110_disp_oimm_ofuncs;
+extern struct nv50_disp_chan_impl gf110_disp_curs_ofuncs;
+extern struct nvkm_ofuncs gf110_disp_main_ofuncs;
+extern struct nvkm_oclass gf110_disp_cclass;
+void gf110_disp_intr_supervisor(struct work_struct *);
+void gf110_disp_intr(struct nvkm_subdev *);
+extern const struct nvkm_event_func gf110_disp_vblank_func;
+
+extern const struct nv50_disp_mthd_chan gk104_disp_core_mthd_chan;
+extern const struct nv50_disp_mthd_chan gk104_disp_ovly_mthd_chan;
 
 extern struct nvkm_output_dp_impl nv50_pior_dp_impl;
-extern struct nouveau_oclass *nv50_disp_outp_sclass[];
+extern struct nvkm_oclass *nv50_disp_outp_sclass[];
 
-extern struct nvkm_output_dp_impl nv94_sor_dp_impl;
-int nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int);
-extern struct nouveau_oclass *nv94_disp_outp_sclass[];
+extern struct nvkm_output_dp_impl g94_sor_dp_impl;
+int g94_sor_dp_lnk_pwr(struct nvkm_output_dp *, int);
+extern struct nvkm_oclass *g94_disp_outp_sclass[];
 
-extern struct nvkm_output_dp_impl nvd0_sor_dp_impl;
-int nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool);
-extern struct nouveau_oclass *nvd0_disp_outp_sclass[];
+extern struct nvkm_output_dp_impl gf110_sor_dp_impl;
+int gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *, int, int, bool);
+extern struct nvkm_oclass *gf110_disp_outp_sclass[];
 
 void gm204_sor_magic(struct nvkm_output *outp);
 extern struct nvkm_output_dp_impl gm204_sor_dp_impl;
-
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.c

@@ -21,57 +21,58 @@
  *
  * Authors: Ben Skeggs
  */
+#include "outp.h"
+#include "priv.h"
 
-#include <subdev/i2c.h>
 #include <subdev/bios.h>
 #include <subdev/bios/conn.h>
-
-#include "outp.h"
+#include <subdev/bios/dcb.h>
+#include <subdev/i2c.h>
 
 int
-_nvkm_output_fini(struct nouveau_object *object, bool suspend)
+_nvkm_output_fini(struct nvkm_object *object, bool suspend)
 {
 	struct nvkm_output *outp = (void *)object;
 	nv_ofuncs(outp->conn)->fini(nv_object(outp->conn), suspend);
-	return nouveau_object_fini(&outp->base, suspend);
+	return nvkm_object_fini(&outp->base, suspend);
 }
 
 int
-_nvkm_output_init(struct nouveau_object *object)
+_nvkm_output_init(struct nvkm_object *object)
 {
 	struct nvkm_output *outp = (void *)object;
-	int ret = nouveau_object_init(&outp->base);
+	int ret = nvkm_object_init(&outp->base);
 	if (ret == 0)
 		nv_ofuncs(outp->conn)->init(nv_object(outp->conn));
 	return 0;
 }
 
 void
-_nvkm_output_dtor(struct nouveau_object *object)
+_nvkm_output_dtor(struct nvkm_object *object)
 {
 	struct nvkm_output *outp = (void *)object;
 	list_del(&outp->head);
-	nouveau_object_ref(NULL, (void *)&outp->conn);
-	nouveau_object_destroy(&outp->base);
+	nvkm_object_ref(NULL, (void *)&outp->conn);
+	nvkm_object_destroy(&outp->base);
 }
 
 int
-nvkm_output_create_(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass,
+nvkm_output_create_(struct nvkm_object *parent,
+		    struct nvkm_object *engine,
+		    struct nvkm_oclass *oclass,
 		    struct dcb_output *dcbE, int index,
 		    int length, void **pobject)
 {
-	struct nouveau_disp *disp = nouveau_disp(parent);
-	struct nouveau_bios *bios = nouveau_bios(parent);
-	struct nouveau_i2c *i2c = nouveau_i2c(parent);
+	struct nvkm_disp *disp = nvkm_disp(parent);
+	struct nvkm_bios *bios = nvkm_bios(parent);
+	struct nvkm_i2c *i2c = nvkm_i2c(parent);
 	struct nvbios_connE connE;
 	struct nvkm_output *outp;
 	u8  ver, hdr;
 	u32 data;
 	int ret;
 
-	ret = nouveau_object_create_(parent, engine, oclass, 0, length, pobject);
+	ret = nvkm_object_create_(parent, engine, oclass, 0, length, pobject);
 	outp = *pobject;
 	if (ret)
 		return ret;
@@ -98,9 +99,9 @@ nvkm_output_create_(struct nouveau_object *parent,
 		connE.type = DCB_CONNECTOR_NONE;
 	}
 
-	ret = nouveau_object_ctor(parent, NULL, nvkm_connector_oclass,
-				 &connE, outp->info.connector,
-				 (struct nouveau_object **)&outp->conn);
+	ret = nvkm_object_ctor(parent, NULL, nvkm_connector_oclass,
+			       &connE, outp->info.connector,
+			       (struct nvkm_object **)&outp->conn);
 	if (ret < 0) {
 		ERR("error %d creating connector, disabling\n", ret);
 		return ret;
@@ -111,10 +112,10 @@ nvkm_output_create_(struct nouveau_object *parent,
 }
 
 int
-_nvkm_output_ctor(struct nouveau_object *parent,
-		  struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *dcbE, u32 index,
-		  struct nouveau_object **pobject)
+_nvkm_output_ctor(struct nvkm_object *parent,
+		  struct nvkm_object *engine,
+		  struct nvkm_oclass *oclass, void *dcbE, u32 index,
+		  struct nvkm_object **pobject)
 {
 	struct nvkm_output *outp;
 	int ret;
@@ -127,11 +128,11 @@ _nvkm_output_ctor(struct nouveau_object *parent,
 	return 0;
 }
 
-struct nouveau_oclass *
+struct nvkm_oclass *
 nvkm_output_oclass = &(struct nvkm_output_impl) {
 	.base = {
 		.handle = 0,
-		.ofuncs = &(struct nouveau_ofuncs) {
+		.ofuncs = &(struct nvkm_ofuncs) {
 			.ctor = _nvkm_output_ctor,
 			.dtor = _nvkm_output_dtor,
 			.init = _nvkm_output_init,

drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.h

@@ -1,18 +1,20 @@
 #ifndef __NVKM_DISP_OUTP_H__
 #define __NVKM_DISP_OUTP_H__
+#include <core/object.h>
 
-#include "priv.h"
+#include <subdev/bios.h>
+#include <subdev/bios/dcb.h>
 
 struct nvkm_output {
-	struct nouveau_object base;
+	struct nvkm_object base;
 	struct list_head head;
 
 	struct dcb_output info;
 	int index;
 	int or;
 
-	struct nouveau_i2c_port *port;
-	struct nouveau_i2c_port *edid;
+	struct nvkm_i2c_port *port;
+	struct nvkm_i2c_port *edid;
 
 	struct nvkm_connector *conn;
 };
@@ -32,19 +34,19 @@ struct nvkm_output {
 	_nvkm_output_fini(nv_object(_outp), (s));                              \
 })
 
-int nvkm_output_create_(struct nouveau_object *, struct nouveau_object *,
-			struct nouveau_oclass *, struct dcb_output *,
+int nvkm_output_create_(struct nvkm_object *, struct nvkm_object *,
+			struct nvkm_oclass *, struct dcb_output *,
 			int, int, void **);
 
-int  _nvkm_output_ctor(struct nouveau_object *, struct nouveau_object *,
-		       struct nouveau_oclass *, void *, u32,
-		       struct nouveau_object **);
-void _nvkm_output_dtor(struct nouveau_object *);
-int  _nvkm_output_init(struct nouveau_object *);
-int  _nvkm_output_fini(struct nouveau_object *, bool);
+int  _nvkm_output_ctor(struct nvkm_object *, struct nvkm_object *,
+		       struct nvkm_oclass *, void *, u32,
+		       struct nvkm_object **);
+void _nvkm_output_dtor(struct nvkm_object *);
+int  _nvkm_output_init(struct nvkm_object *);
+int  _nvkm_output_fini(struct nvkm_object *, bool);
 
 struct nvkm_output_impl {
-	struct nouveau_oclass base;
+	struct nvkm_oclass base;
 };
 
 #ifndef MSG
@@ -56,5 +58,4 @@ struct nvkm_output_impl {
 #define DBG(f,a...) MSG(debug, f, ##a)
 #define ERR(f,a...) MSG(error, f, ##a)
 #endif
-
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.c

@@ -21,15 +21,14 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <core/os.h>
-#include <nvif/event.h>
-
-#include <subdev/i2c.h>
-
 #include "outpdp.h"
 #include "conn.h"
 #include "dport.h"
+#include "priv.h"
+
+#include <subdev/i2c.h>
+
+#include <nvif/event.h>
 
 int
 nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait)
@@ -105,17 +104,17 @@ done:
 static void
 nvkm_output_dp_enable(struct nvkm_output_dp *outp, bool present)
 {
-	struct nouveau_i2c_port *port = outp->base.edid;
+	struct nvkm_i2c_port *port = outp->base.edid;
 	if (present) {
 		if (!outp->present) {
-			nouveau_i2c(port)->acquire_pad(port, 0);
+			nvkm_i2c(port)->acquire_pad(port, 0);
 			DBG("aux power -> always\n");
 			outp->present = true;
 		}
 		nvkm_output_dp_train(&outp->base, 0, true);
 	} else {
 		if (outp->present) {
-			nouveau_i2c(port)->release_pad(port);
+			nvkm_i2c(port)->release_pad(port);
 			DBG("aux power -> demand\n");
 			outp->present = false;
 		}
@@ -126,13 +125,13 @@ nvkm_output_dp_enable(struct nvkm_output_dp *outp, bool present)
 static void
 nvkm_output_dp_detect(struct nvkm_output_dp *outp)
 {
-	struct nouveau_i2c_port *port = outp->base.edid;
-	int ret = nouveau_i2c(port)->acquire_pad(port, 0);
+	struct nvkm_i2c_port *port = outp->base.edid;
+	int ret = nvkm_i2c(port)->acquire_pad(port, 0);
 	if (ret == 0) {
 		ret = nv_rdaux(outp->base.edid, DPCD_RC00_DPCD_REV,
 			       outp->dpcd, sizeof(outp->dpcd));
 		nvkm_output_dp_enable(outp, ret == 0);
-		nouveau_i2c(port)->release_pad(port);
+		nvkm_i2c(port)->release_pad(port);
 	}
 }
 
@@ -141,7 +140,7 @@ nvkm_output_dp_hpd(struct nvkm_notify *notify)
 {
 	struct nvkm_connector *conn = container_of(notify, typeof(*conn), hpd);
 	struct nvkm_output_dp *outp;
-	struct nouveau_disp *disp = nouveau_disp(conn);
+	struct nvkm_disp *disp = nvkm_disp(conn);
 	const struct nvkm_i2c_ntfy_rep *line = notify->data;
 	struct nvif_notify_conn_rep_v0 rep = {};
 
@@ -170,7 +169,7 @@ static int
 nvkm_output_dp_irq(struct nvkm_notify *notify)
 {
 	struct nvkm_output_dp *outp = container_of(notify, typeof(*outp), irq);
-	struct nouveau_disp *disp = nouveau_disp(outp);
+	struct nvkm_disp *disp = nvkm_disp(outp);
 	const struct nvkm_i2c_ntfy_rep *line = notify->data;
 	struct nvif_notify_conn_rep_v0 rep = {
 		.mask = NVIF_NOTIFY_CONN_V0_IRQ,
@@ -185,7 +184,7 @@ nvkm_output_dp_irq(struct nvkm_notify *notify)
 }
 
 int
-_nvkm_output_dp_fini(struct nouveau_object *object, bool suspend)
+_nvkm_output_dp_fini(struct nvkm_object *object, bool suspend)
 {
 	struct nvkm_output_dp *outp = (void *)object;
 	nvkm_notify_put(&outp->irq);
@@ -194,7 +193,7 @@ _nvkm_output_dp_fini(struct nouveau_object *object, bool suspend)
 }
 
 int
-_nvkm_output_dp_init(struct nouveau_object *object)
+_nvkm_output_dp_init(struct nvkm_object *object)
 {
 	struct nvkm_output_dp *outp = (void *)object;
 	nvkm_output_dp_detect(outp);
@@ -202,7 +201,7 @@ _nvkm_output_dp_init(struct nouveau_object *object)
 }
 
 void
-_nvkm_output_dp_dtor(struct nouveau_object *object)
+_nvkm_output_dp_dtor(struct nvkm_object *object)
 {
 	struct nvkm_output_dp *outp = (void *)object;
 	nvkm_notify_fini(&outp->irq);
@@ -210,14 +209,14 @@ _nvkm_output_dp_dtor(struct nouveau_object *object)
 }
 
 int
-nvkm_output_dp_create_(struct nouveau_object *parent,
-		       struct nouveau_object *engine,
-		       struct nouveau_oclass *oclass,
+nvkm_output_dp_create_(struct nvkm_object *parent,
+		       struct nvkm_object *engine,
+		       struct nvkm_oclass *oclass,
 		       struct dcb_output *info, int index,
 		       int length, void **pobject)
 {
-	struct nouveau_bios *bios = nouveau_bios(parent);
-	struct nouveau_i2c *i2c = nouveau_i2c(parent);
+	struct nvkm_bios *bios = nvkm_bios(parent);
+	struct nvkm_i2c *i2c = nvkm_i2c(parent);
 	struct nvkm_output_dp *outp;
 	u8  hdr, cnt, len;
 	u32 data;
@@ -249,7 +248,7 @@ nvkm_output_dp_create_(struct nouveau_object *parent,
 	DBG("bios dp %02x %02x %02x %02x\n", outp->version, hdr, cnt, len);
 
 	/* link training */
-	INIT_WORK(&outp->lt.work, nouveau_dp_train);
+	INIT_WORK(&outp->lt.work, nvkm_dp_train);
 	init_waitqueue_head(&outp->lt.wait);
 	atomic_set(&outp->lt.done, 0);
 
@@ -285,10 +284,10 @@ nvkm_output_dp_create_(struct nouveau_object *parent,
 }
 
 int
-_nvkm_output_dp_ctor(struct nouveau_object *parent,
-		     struct nouveau_object *engine,
-		     struct nouveau_oclass *oclass, void *info, u32 index,
-		     struct nouveau_object **pobject)
+_nvkm_output_dp_ctor(struct nvkm_object *parent,
+		     struct nvkm_object *engine,
+		     struct nvkm_oclass *oclass, void *info, u32 index,
+		     struct nvkm_object **pobject)
 {
 	struct nvkm_output_dp *outp;
 	int ret;

drivers/gpu/drm/nouveau/nvkm/engine/disp/outpdp.h

@@ -1,12 +1,11 @@
 #ifndef __NVKM_DISP_OUTP_DP_H__
 #define __NVKM_DISP_OUTP_DP_H__
+#include "outp.h"
 
 #include <core/notify.h>
 #include <subdev/bios.h>
 #include <subdev/bios/dp.h>
 
-#include "outp.h"
-
 struct nvkm_output_dp {
 	struct nvkm_output base;
 
@@ -39,16 +38,16 @@ struct nvkm_output_dp {
 	_nvkm_output_dp_fini(nv_object(_outp), (s));                           \
 })
 
-int nvkm_output_dp_create_(struct nouveau_object *, struct nouveau_object *,
-			   struct nouveau_oclass *, struct dcb_output *,
+int nvkm_output_dp_create_(struct nvkm_object *, struct nvkm_object *,
+			   struct nvkm_oclass *, struct dcb_output *,
 			   int, int, void **);
 
-int  _nvkm_output_dp_ctor(struct nouveau_object *, struct nouveau_object *,
-			  struct nouveau_oclass *, void *, u32,
-			  struct nouveau_object **);
-void _nvkm_output_dp_dtor(struct nouveau_object *);
-int  _nvkm_output_dp_init(struct nouveau_object *);
-int  _nvkm_output_dp_fini(struct nouveau_object *, bool);
+int  _nvkm_output_dp_ctor(struct nvkm_object *, struct nvkm_object *,
+			  struct nvkm_oclass *, void *, u32,
+			  struct nvkm_object **);
+void _nvkm_output_dp_dtor(struct nvkm_object *);
+int  _nvkm_output_dp_init(struct nvkm_object *);
+int  _nvkm_output_dp_fini(struct nvkm_object *, bool);
 
 struct nvkm_output_dp_impl {
 	struct nvkm_output_impl base;
@@ -59,5 +58,4 @@ struct nvkm_output_dp_impl {
 };
 
 int nvkm_output_dp_train(struct nvkm_output *, u32 rate, bool wait);
-
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/piornv50.c

@@ -21,29 +21,27 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
+#include "outpdp.h"
 
 #include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/timer.h>
 #include <subdev/i2c.h>
+#include <subdev/timer.h>
 
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
 
 /******************************************************************************
  * TMDS
  *****************************************************************************/
 
 static int
-nv50_pior_tmds_ctor(struct nouveau_object *parent,
-		    struct nouveau_object *engine,
-		    struct nouveau_oclass *oclass, void *info, u32 index,
-		    struct nouveau_object **pobject)
+nv50_pior_tmds_ctor(struct nvkm_object *parent,
+		    struct nvkm_object *engine,
+		    struct nvkm_oclass *oclass, void *info, u32 index,
+		    struct nvkm_object **pobject)
 {
-	struct nouveau_i2c *i2c = nouveau_i2c(parent);
+	struct nvkm_i2c *i2c = nvkm_i2c(parent);
 	struct nvkm_output *outp;
 	int ret;
 
@@ -59,7 +57,7 @@ nv50_pior_tmds_ctor(struct nouveau_object *parent,
 struct nvkm_output_impl
 nv50_pior_tmds_impl = {
 	.base.handle = DCB_OUTPUT_TMDS | 0x0100,
-	.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv50_pior_tmds_ctor,
 		.dtor = _nvkm_output_dtor,
 		.init = _nvkm_output_init,
@@ -74,7 +72,7 @@ nv50_pior_tmds_impl = {
 static int
 nv50_pior_dp_pattern(struct nvkm_output_dp *outp, int pattern)
 {
-	struct nouveau_i2c_port *port = outp->base.edid;
+	struct nvkm_i2c_port *port = outp->base.edid;
 	if (port && port->func->pattern)
 		return port->func->pattern(port, pattern);
 	return port ? 0 : -ENODEV;
@@ -89,7 +87,7 @@ nv50_pior_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
 static int
 nv50_pior_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
 {
-	struct nouveau_i2c_port *port = outp->base.edid;
+	struct nvkm_i2c_port *port = outp->base.edid;
 	if (port && port->func->lnk_ctl)
 		return port->func->lnk_ctl(port, nr, bw, ef);
 	return port ? 0 : -ENODEV;
@@ -98,19 +96,19 @@ nv50_pior_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
 static int
 nv50_pior_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
 {
-	struct nouveau_i2c_port *port = outp->base.edid;
+	struct nvkm_i2c_port *port = outp->base.edid;
 	if (port && port->func->drv_ctl)
 		return port->func->drv_ctl(port, ln, vs, pe);
 	return port ? 0 : -ENODEV;
 }
 
 static int
-nv50_pior_dp_ctor(struct nouveau_object *parent,
-		  struct nouveau_object *engine,
-		  struct nouveau_oclass *oclass, void *info, u32 index,
-		  struct nouveau_object **pobject)
+nv50_pior_dp_ctor(struct nvkm_object *parent,
+		  struct nvkm_object *engine,
+		  struct nvkm_oclass *oclass, void *info, u32 index,
+		  struct nvkm_object **pobject)
 {
-	struct nouveau_i2c *i2c = nouveau_i2c(parent);
+	struct nvkm_i2c *i2c = nvkm_i2c(parent);
 	struct nvkm_output_dp *outp;
 	int ret;
 
@@ -127,7 +125,7 @@ nv50_pior_dp_ctor(struct nouveau_object *parent,
 struct nvkm_output_dp_impl
 nv50_pior_dp_impl = {
 	.base.base.handle = DCB_OUTPUT_DP | 0x0010,
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = nv50_pior_dp_ctor,
 		.dtor = _nvkm_output_dp_dtor,
 		.init = _nvkm_output_dp_init,

drivers/gpu/drm/nouveau/nvkm/engine/disp/priv.h

@@ -1,48 +1,42 @@
 #ifndef __NVKM_DISP_PRIV_H__
 #define __NVKM_DISP_PRIV_H__
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/conn.h>
-
 #include <engine/disp.h>
 
-struct nouveau_disp_impl {
-	struct nouveau_oclass base;
-	struct nouveau_oclass **outp;
-	struct nouveau_oclass **conn;
+struct nvkm_disp_impl {
+	struct nvkm_oclass base;
+	struct nvkm_oclass **outp;
+	struct nvkm_oclass **conn;
 	const struct nvkm_event_func *vblank;
 };
 
-#define nouveau_disp_create(p,e,c,h,i,x,d)                                     \
-	nouveau_disp_create_((p), (e), (c), (h), (i), (x),                     \
+#define nvkm_disp_create(p,e,c,h,i,x,d)                                     \
+	nvkm_disp_create_((p), (e), (c), (h), (i), (x),                     \
 			     sizeof(**d), (void **)d)
-#define nouveau_disp_destroy(d) ({                                             \
-	struct nouveau_disp *disp = (d);                                       \
-	_nouveau_disp_dtor(nv_object(disp));                                   \
+#define nvkm_disp_destroy(d) ({                                             \
+	struct nvkm_disp *disp = (d);                                       \
+	_nvkm_disp_dtor(nv_object(disp));                                   \
 })
-#define nouveau_disp_init(d) ({                                                \
-	struct nouveau_disp *disp = (d);                                       \
-	_nouveau_disp_init(nv_object(disp));                                   \
+#define nvkm_disp_init(d) ({                                                \
+	struct nvkm_disp *disp = (d);                                       \
+	_nvkm_disp_init(nv_object(disp));                                   \
 })
-#define nouveau_disp_fini(d,s) ({                                              \
-	struct nouveau_disp *disp = (d);                                       \
-	_nouveau_disp_fini(nv_object(disp), (s));                              \
+#define nvkm_disp_fini(d,s) ({                                              \
+	struct nvkm_disp *disp = (d);                                       \
+	_nvkm_disp_fini(nv_object(disp), (s));                              \
 })
 
-int  nouveau_disp_create_(struct nouveau_object *, struct nouveau_object *,
-			  struct nouveau_oclass *, int heads,
+int  nvkm_disp_create_(struct nvkm_object *, struct nvkm_object *,
+			  struct nvkm_oclass *, int heads,
 			  const char *, const char *, int, void **);
-void _nouveau_disp_dtor(struct nouveau_object *);
-int  _nouveau_disp_init(struct nouveau_object *);
-int  _nouveau_disp_fini(struct nouveau_object *, bool);
-
-extern struct nouveau_oclass *nvkm_output_oclass;
-extern struct nouveau_oclass *nvkm_connector_oclass;
+void _nvkm_disp_dtor(struct nvkm_object *);
+int  _nvkm_disp_init(struct nvkm_object *);
+int  _nvkm_disp_fini(struct nvkm_object *, bool);
 
-int  nouveau_disp_vblank_ctor(struct nouveau_object *, void *data, u32 size,
-			      struct nvkm_notify *);
-void nouveau_disp_vblank(struct nouveau_disp *, int head);
-int  nouveau_disp_ntfy(struct nouveau_object *, u32, struct nvkm_event **);
+extern struct nvkm_oclass *nvkm_output_oclass;
+extern struct nvkm_oclass *nvkm_connector_oclass;
 
+int  nvkm_disp_vblank_ctor(struct nvkm_object *, void *data, u32 size,
+			   struct nvkm_notify *);
+void nvkm_disp_vblank(struct nvkm_disp *, int head);
+int  nvkm_disp_ntfy(struct nvkm_object *, u32, struct nvkm_event **);
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv94.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/sorg94.c

@@ -21,59 +21,53 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <core/os.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/init.h>
-#include <subdev/timer.h>
-
 #include "nv50.h"
 #include "outpdp.h"
 
+#include <core/device.h>
+#include <subdev/timer.h>
+
 static inline u32
-nv94_sor_soff(struct nvkm_output_dp *outp)
+g94_sor_soff(struct nvkm_output_dp *outp)
 {
 	return (ffs(outp->base.info.or) - 1) * 0x800;
 }
 
 static inline u32
-nv94_sor_loff(struct nvkm_output_dp *outp)
+g94_sor_loff(struct nvkm_output_dp *outp)
 {
-	return nv94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
+	return g94_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
 }
 
 static inline u32
-nv94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
+g94_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
 {
-	static const u8 nvaf[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
-	static const u8 nv94[] = { 16, 8, 0, 24 };
+	static const u8 mcp89[] = { 24, 16, 8, 0 }; /* thanks, apple.. */
+	static const u8 g94[] = { 16, 8, 0, 24 };
 	if (nv_device(priv)->chipset == 0xaf)
-		return nvaf[lane];
-	return nv94[lane];
+		return mcp89[lane];
+	return g94[lane];
 }
 
 static int
-nv94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
+g94_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
 {
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 loff = nv94_sor_loff(outp);
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+	const u32 loff = g94_sor_loff(outp);
 	nv_mask(priv, 0x61c10c + loff, 0x0f000000, pattern << 24);
 	return 0;
 }
 
 int
-nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
+g94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
 {
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 soff = nv94_sor_soff(outp);
-	const u32 loff = nv94_sor_loff(outp);
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+	const u32 soff = g94_sor_soff(outp);
+	const u32 loff = g94_sor_loff(outp);
 	u32 mask = 0, i;
 
 	for (i = 0; i < nr; i++)
-		mask |= 1 << (nv94_sor_dp_lane_map(priv, i) >> 3);
+		mask |= 1 << (g94_sor_dp_lane_map(priv, i) >> 3);
 
 	nv_mask(priv, 0x61c130 + loff, 0x0000000f, mask);
 	nv_mask(priv, 0x61c034 + soff, 0x80000000, 0x80000000);
@@ -82,11 +76,11 @@ nv94_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
 }
 
 static int
-nv94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
+g94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
 {
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 soff = nv94_sor_soff(outp);
-	const u32 loff = nv94_sor_loff(outp);
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+	const u32 soff = g94_sor_soff(outp);
+	const u32 loff = g94_sor_loff(outp);
 	u32 dpctrl = 0x00000000;
 	u32 clksor = 0x00000000;
 
@@ -102,12 +96,12 @@ nv94_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
 }
 
 static int
-nv94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
+g94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
 {
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	const u32 shift = nv94_sor_dp_lane_map(priv, ln);
-	const u32 loff = nv94_sor_loff(outp);
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+	struct nvkm_bios *bios = nvkm_bios(priv);
+	const u32 shift = g94_sor_dp_lane_map(priv, ln);
+	const u32 loff = g94_sor_loff(outp);
 	u32 addr, data[3];
 	u8  ver, hdr, cnt, len;
 	struct nvbios_dpout info;
@@ -136,16 +130,16 @@ nv94_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
 }
 
 struct nvkm_output_dp_impl
-nv94_sor_dp_impl = {
+g94_sor_dp_impl = {
 	.base.base.handle = DCB_OUTPUT_DP,
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = _nvkm_output_dp_ctor,
 		.dtor = _nvkm_output_dp_dtor,
 		.init = _nvkm_output_dp_init,
 		.fini = _nvkm_output_dp_fini,
 	},
-	.pattern = nv94_sor_dp_pattern,
-	.lnk_pwr = nv94_sor_dp_lnk_pwr,
-	.lnk_ctl = nv94_sor_dp_lnk_ctl,
-	.drv_ctl = nv94_sor_dp_drv_ctl,
+	.pattern = g94_sor_dp_pattern,
+	.lnk_pwr = g94_sor_dp_lnk_pwr,
+	.lnk_ctl = g94_sor_dp_lnk_ctl,
+	.drv_ctl = g94_sor_dp_drv_ctl,
 };

drivers/gpu/drm/nouveau/nvkm/engine/disp/sornvd0.c → drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf110.c

@@ -21,51 +21,43 @@
  *
  * Authors: Ben Skeggs
  */
-
-#include <core/os.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/init.h>
-#include <subdev/timer.h>
-
 #include "nv50.h"
+#include "outpdp.h"
 
 static inline u32
-nvd0_sor_soff(struct nvkm_output_dp *outp)
+gf110_sor_soff(struct nvkm_output_dp *outp)
 {
 	return (ffs(outp->base.info.or) - 1) * 0x800;
 }
 
 static inline u32
-nvd0_sor_loff(struct nvkm_output_dp *outp)
+gf110_sor_loff(struct nvkm_output_dp *outp)
 {
-	return nvd0_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
+	return gf110_sor_soff(outp) + !(outp->base.info.sorconf.link & 1) * 0x80;
 }
 
 static inline u32
-nvd0_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
+gf110_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
 {
-	static const u8 nvd0[] = { 16, 8, 0, 24 };
-	return nvd0[lane];
+	static const u8 gf110[] = { 16, 8, 0, 24 };
+	return gf110[lane];
 }
 
 static int
-nvd0_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
+gf110_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
 {
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 loff = nvd0_sor_loff(outp);
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+	const u32 loff = gf110_sor_loff(outp);
 	nv_mask(priv, 0x61c110 + loff, 0x0f0f0f0f, 0x01010101 * pattern);
 	return 0;
 }
 
 int
-nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
+gf110_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
 {
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	const u32 soff = nvd0_sor_soff(outp);
-	const u32 loff = nvd0_sor_loff(outp);
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+	const u32 soff = gf110_sor_soff(outp);
+	const u32 loff = gf110_sor_loff(outp);
 	u32 dpctrl = 0x00000000;
 	u32 clksor = 0x00000000;
 
@@ -80,12 +72,13 @@ nvd0_sor_dp_lnk_ctl(struct nvkm_output_dp *outp, int nr, int bw, bool ef)
 }
 
 static int
-nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
+gf110_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
+		     int ln, int vs, int pe, int pc)
 {
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(priv);
-	const u32 shift = nvd0_sor_dp_lane_map(priv, ln);
-	const u32 loff = nvd0_sor_loff(outp);
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+	struct nvkm_bios *bios = nvkm_bios(priv);
+	const u32 shift = gf110_sor_dp_lane_map(priv, ln);
+	const u32 loff = gf110_sor_loff(outp);
 	u32 addr, data[4];
 	u8  ver, hdr, cnt, len;
 	struct nvbios_dpout info;
@@ -93,12 +86,12 @@ nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
 
 	addr = nvbios_dpout_match(bios, outp->base.info.hasht,
 					outp->base.info.hashm,
-				 &ver, &hdr, &cnt, &len, &info);
+				  &ver, &hdr, &cnt, &len, &info);
 	if (!addr)
 		return -ENODEV;
 
 	addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
-				 &ver, &hdr, &cnt, &len, &ocfg);
+				  &ver, &hdr, &cnt, &len, &ocfg);
 	if (!addr)
 		return -EINVAL;
 
@@ -116,16 +109,16 @@ nvd0_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
 }
 
 struct nvkm_output_dp_impl
-nvd0_sor_dp_impl = {
+gf110_sor_dp_impl = {
 	.base.base.handle = DCB_OUTPUT_DP,
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = _nvkm_output_dp_ctor,
 		.dtor = _nvkm_output_dp_dtor,
 		.init = _nvkm_output_dp_init,
 		.fini = _nvkm_output_dp_fini,
 	},
-	.pattern = nvd0_sor_dp_pattern,
-	.lnk_pwr = nv94_sor_dp_lnk_pwr,
-	.lnk_ctl = nvd0_sor_dp_lnk_ctl,
-	.drv_ctl = nvd0_sor_dp_drv_ctl,
+	.pattern = gf110_sor_dp_pattern,
+	.lnk_pwr = g94_sor_dp_lnk_pwr,
+	.lnk_ctl = gf110_sor_dp_lnk_ctl,
+	.drv_ctl = gf110_sor_dp_drv_ctl,
 };

drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgm204.c

@@ -21,17 +21,11 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
+#include "outpdp.h"
 
-#include <core/os.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
-#include <subdev/bios/dp.h>
-#include <subdev/bios/init.h>
 #include <subdev/timer.h>
 
-#include "nv50.h"
-
 static inline u32
 gm204_sor_soff(struct nvkm_output_dp *outp)
 {
@@ -47,7 +41,7 @@ gm204_sor_loff(struct nvkm_output_dp *outp)
 void
 gm204_sor_magic(struct nvkm_output *outp)
 {
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
 	const u32 soff = outp->or * 0x100;
 	const u32 data = outp->or + 1;
 	if (outp->info.sorconf.link & 1)
@@ -65,7 +59,7 @@ gm204_sor_dp_lane_map(struct nv50_disp_priv *priv, u8 lane)
 static int
 gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
 {
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
 	const u32 soff = gm204_sor_soff(outp);
 	const u32 data = 0x01010101 * pattern;
 	if (outp->base.info.sorconf.link & 1)
@@ -78,7 +72,7 @@ gm204_sor_dp_pattern(struct nvkm_output_dp *outp, int pattern)
 static int
 gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
 {
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
 	const u32 soff = gm204_sor_soff(outp);
 	const u32 loff = gm204_sor_loff(outp);
 	u32 mask = 0, i;
@@ -93,10 +87,11 @@ gm204_sor_dp_lnk_pwr(struct nvkm_output_dp *outp, int nr)
 }
 
 static int
-gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc)
+gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp,
+		     int ln, int vs, int pe, int pc)
 {
-	struct nv50_disp_priv *priv = (void *)nouveau_disp(outp);
-	struct nouveau_bios *bios = nouveau_bios(priv);
+	struct nv50_disp_priv *priv = (void *)nvkm_disp(outp);
+	struct nvkm_bios *bios = nvkm_bios(priv);
 	const u32 shift = gm204_sor_dp_lane_map(priv, ln);
 	const u32 loff = gm204_sor_loff(outp);
 	u32 addr, data[4];
@@ -106,12 +101,12 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc
 
 	addr = nvbios_dpout_match(bios, outp->base.info.hasht,
 					outp->base.info.hashm,
-				 &ver, &hdr, &cnt, &len, &info);
+				  &ver, &hdr, &cnt, &len, &info);
 	if (!addr)
 		return -ENODEV;
 
 	addr = nvbios_dpcfg_match(bios, addr, pc, vs, pe,
-				 &ver, &hdr, &cnt, &len, &ocfg);
+				  &ver, &hdr, &cnt, &len, &ocfg);
 	if (!addr)
 		return -EINVAL;
 
@@ -131,7 +126,7 @@ gm204_sor_dp_drv_ctl(struct nvkm_output_dp *outp, int ln, int vs, int pe, int pc
 struct nvkm_output_dp_impl
 gm204_sor_dp_impl = {
 	.base.base.handle = DCB_OUTPUT_DP,
-	.base.base.ofuncs = &(struct nouveau_ofuncs) {
+	.base.base.ofuncs = &(struct nvkm_ofuncs) {
 		.ctor = _nvkm_output_dp_ctor,
 		.dtor = _nvkm_output_dp_dtor,
 		.init = _nvkm_output_dp_init,
@@ -139,6 +134,6 @@ gm204_sor_dp_impl = {
 	},
 	.pattern = gm204_sor_dp_pattern,
 	.lnk_pwr = gm204_sor_dp_lnk_pwr,
-	.lnk_ctl = nvd0_sor_dp_lnk_ctl,
+	.lnk_ctl = gf110_sor_dp_lnk_ctl,
 	.drv_ctl = gm204_sor_dp_drv_ctl,
 };

drivers/gpu/drm/nouveau/nvkm/engine/disp/sornv50.c

@@ -21,16 +21,14 @@
  *
  * Authors: Ben Skeggs
  */
+#include "nv50.h"
+#include "outp.h"
 
 #include <core/client.h>
-#include <nvif/unpack.h>
-#include <nvif/class.h>
-
-#include <subdev/bios.h>
-#include <subdev/bios/dcb.h>
 #include <subdev/timer.h>
 
-#include "nv50.h"
+#include <nvif/class.h>
+#include <nvif/unpack.h>
 
 int
 nv50_sor_power(NV50_DISP_MTHD_V1)

drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.c

@@ -21,15 +21,14 @@
  *
  * Authors: Ben Skeggs
  */
+#include <subdev/vga.h>
 
-#include <core/subdev.h>
 #include <core/device.h>
-#include <subdev/vga.h>
 
 u8
 nv_rdport(void *obj, int head, u16 port)
 {
-	struct nouveau_device *device = nv_device(obj);
+	struct nvkm_device *device = nv_device(obj);
 
 	if (device->card_type >= NV_50)
 		return nv_rd08(obj, 0x601000 + port);
@@ -54,7 +53,7 @@ nv_rdport(void *obj, int head, u16 port)
 void
 nv_wrport(void *obj, int head, u16 port, u8 data)
 {
-	struct nouveau_device *device = nv_device(obj);
+	struct nvkm_device *device = nv_device(obj);
 
 	if (device->card_type >= NV_50)
 		nv_wr08(obj, 0x601000 + port, data);
@@ -138,7 +137,7 @@ nv_wrvgai(void *obj, int head, u16 port, u8 index, u8 value)
 bool
 nv_lockvgac(void *obj, bool lock)
 {
-	struct nouveau_device *dev = nv_device(obj);
+	struct nvkm_device *dev = nv_device(obj);
 
 	bool locked = !nv_rdvgac(obj, 0, 0x1f);
 	u8 data = lock ? 0x99 : 0x57;

drivers/gpu/drm/nouveau/nvkm/engine/sw/nv50.c

@@ -23,6 +23,7 @@
  */
 
 #include <core/os.h>
+#include <core/device.h>
 #include <core/engctx.h>
 #include <core/namedb.h>
 #include <core/handle.h>