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@@ -81,7 +81,7 @@ static const struct of_device_id arm_cci_matches[] = {
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#define CCI_PMU_CNTR_MASK ((1ULL << 32) -1)
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-#define CCI_PMU_EVENT_MASK 0xff
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+#define CCI_PMU_EVENT_MASK 0xffUL
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#define CCI_PMU_EVENT_SOURCE(event) ((event >> 5) & 0x7)
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#define CCI_PMU_EVENT_CODE(event) (event & 0x1f)
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@@ -179,12 +179,15 @@ enum cci400_perf_events {
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#define CCI_REV_R1_MASTER_PORT_MIN_EV 0x00
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#define CCI_REV_R1_MASTER_PORT_MAX_EV 0x11
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-static int pmu_validate_hw_event(u8 hw_event)
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+static int pmu_validate_hw_event(unsigned long hw_event)
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{
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u8 ev_source = CCI_PMU_EVENT_SOURCE(hw_event);
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u8 ev_code = CCI_PMU_EVENT_CODE(hw_event);
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int if_type;
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+ if (hw_event & ~CCI_PMU_EVENT_MASK)
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+ return -ENOENT;
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+
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switch (ev_source) {
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case CCI_PORT_S0:
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case CCI_PORT_S1:
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@@ -258,7 +261,6 @@ static void pmu_enable_counter(int idx)
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static void pmu_set_event(int idx, unsigned long event)
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{
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- event &= CCI_PMU_EVENT_MASK;
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pmu_write_register(event, idx, CCI_PMU_EVT_SEL);
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}
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@@ -275,7 +277,7 @@ static int pmu_get_event_idx(struct cci_pmu_hw_events *hw, struct perf_event *ev
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{
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struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
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struct hw_perf_event *hw_event = &event->hw;
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- unsigned long cci_event = hw_event->config_base & CCI_PMU_EVENT_MASK;
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+ unsigned long cci_event = hw_event->config_base;
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int idx;
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if (cci_event == CCI_PMU_CYCLES) {
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@@ -296,7 +298,7 @@ static int pmu_get_event_idx(struct cci_pmu_hw_events *hw, struct perf_event *ev
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static int pmu_map_event(struct perf_event *event)
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{
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int mapping;
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- u8 config = event->attr.config & CCI_PMU_EVENT_MASK;
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+ unsigned long config = event->attr.config;
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if (event->attr.type < PERF_TYPE_MAX)
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return -ENOENT;
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