|
@@ -203,6 +203,7 @@ static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel)
|
|
|
static void config_sata_phy(u64 regbase)
|
|
|
{
|
|
|
u32 port, i, reg;
|
|
|
+ u8 val;
|
|
|
|
|
|
for (port = 0; port < 2; port++) {
|
|
|
for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++)
|
|
@@ -210,6 +211,18 @@ static void config_sata_phy(u64 regbase)
|
|
|
|
|
|
for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++)
|
|
|
write_phy_reg(regbase, reg, port, sata_phy_config2[i]);
|
|
|
+
|
|
|
+ /* Fix for PHY link up failures at lower temperatures */
|
|
|
+ write_phy_reg(regbase, 0x800F, port, 0x1f);
|
|
|
+
|
|
|
+ val = read_phy_reg(regbase, 0x0029, port);
|
|
|
+ write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1));
|
|
|
+
|
|
|
+ val = read_phy_reg(regbase, 0x0056, port);
|
|
|
+ write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3));
|
|
|
+
|
|
|
+ val = read_phy_reg(regbase, 0x0018, port);
|
|
|
+ write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0));
|
|
|
}
|
|
|
}
|
|
|
|