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@@ -4579,9 +4579,9 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
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mqd->compute_misc_reserved = 0x00000003;
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if (!(adev->flags & AMD_IS_APU)) {
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mqd->dynamic_cu_mask_addr_lo = lower_32_bits(ring->mqd_gpu_addr
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- + offsetof(struct vi_mqd_allocation, dyamic_cu_mask));
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+ + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
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mqd->dynamic_cu_mask_addr_hi = upper_32_bits(ring->mqd_gpu_addr
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- + offsetof(struct vi_mqd_allocation, dyamic_cu_mask));
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+ + offsetof(struct vi_mqd_allocation, dynamic_cu_mask));
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}
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eop_base_addr = ring->eop_gpu_addr >> 8;
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mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
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@@ -4768,8 +4768,8 @@ static int gfx_v8_0_kiq_init_queue(struct amdgpu_ring *ring)
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mutex_unlock(&adev->srbm_mutex);
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} else {
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memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
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- ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF;
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- ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF;
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+ ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
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+ ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
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mutex_lock(&adev->srbm_mutex);
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vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
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gfx_v8_0_mqd_init(ring);
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@@ -4792,8 +4792,8 @@ static int gfx_v8_0_kcq_init_queue(struct amdgpu_ring *ring)
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if (!adev->gfx.in_reset && !adev->gfx.in_suspend) {
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memset((void *)mqd, 0, sizeof(struct vi_mqd_allocation));
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- ((struct vi_mqd_allocation *)mqd)->dyamic_cu_mask = 0xFFFFFFFF;
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- ((struct vi_mqd_allocation *)mqd)->dyamic_rb_mask = 0xFFFFFFFF;
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+ ((struct vi_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
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+ ((struct vi_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
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mutex_lock(&adev->srbm_mutex);
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vi_srbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
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gfx_v8_0_mqd_init(ring);
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