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@@ -213,7 +213,7 @@ static void mce_threshold_block_init(struct threshold_block *b, int offset)
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threshold_restart_bank(&tr);
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threshold_restart_bank(&tr);
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};
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};
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-static int setup_APIC_mce(int reserved, int new)
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+static int setup_APIC_mce_threshold(int reserved, int new)
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{
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{
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if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
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if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
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APIC_EILVT_MSG_FIX, 0))
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APIC_EILVT_MSG_FIX, 0))
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@@ -302,7 +302,7 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c)
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b.interrupt_enable = 1;
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b.interrupt_enable = 1;
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new = (high & MASK_LVTOFF_HI) >> 20;
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new = (high & MASK_LVTOFF_HI) >> 20;
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- offset = setup_APIC_mce(offset, new);
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+ offset = setup_APIC_mce_threshold(offset, new);
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if ((offset == new) &&
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if ((offset == new) &&
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(mce_threshold_vector != amd_threshold_interrupt))
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(mce_threshold_vector != amd_threshold_interrupt))
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