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@@ -298,6 +298,7 @@ struct sdma_engine;
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* @event_id1 for channels that use 2 events
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* @event_id1 for channels that use 2 events
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* @word_size peripheral access size
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* @word_size peripheral access size
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* @buf_tail ID of the buffer that was processed
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* @buf_tail ID of the buffer that was processed
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+ * @buf_ptail ID of the previous buffer that was processed
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* @num_bd max NUM_BD. number of descriptors currently handling
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* @num_bd max NUM_BD. number of descriptors currently handling
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*/
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*/
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struct sdma_channel {
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struct sdma_channel {
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@@ -309,6 +310,7 @@ struct sdma_channel {
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unsigned int event_id1;
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unsigned int event_id1;
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enum dma_slave_buswidth word_size;
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enum dma_slave_buswidth word_size;
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unsigned int buf_tail;
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unsigned int buf_tail;
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+ unsigned int buf_ptail;
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unsigned int num_bd;
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unsigned int num_bd;
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unsigned int period_len;
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unsigned int period_len;
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struct sdma_buffer_descriptor *bd;
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struct sdma_buffer_descriptor *bd;
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@@ -700,6 +702,8 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac)
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sdmac->chn_real_count = bd->mode.count;
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sdmac->chn_real_count = bd->mode.count;
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bd->mode.status |= BD_DONE;
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bd->mode.status |= BD_DONE;
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bd->mode.count = sdmac->period_len;
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bd->mode.count = sdmac->period_len;
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+ sdmac->buf_ptail = sdmac->buf_tail;
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+ sdmac->buf_tail = (sdmac->buf_tail + 1) % sdmac->num_bd;
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/*
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/*
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* The callback is called from the interrupt context in order
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* The callback is called from the interrupt context in order
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@@ -710,9 +714,6 @@ static void sdma_update_channel_loop(struct sdma_channel *sdmac)
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dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
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dmaengine_desc_get_callback_invoke(&sdmac->desc, NULL);
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- sdmac->buf_tail++;
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- sdmac->buf_tail %= sdmac->num_bd;
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-
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if (error)
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if (error)
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sdmac->status = old_status;
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sdmac->status = old_status;
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}
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}
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@@ -1186,6 +1187,8 @@ static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
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sdmac->flags = 0;
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sdmac->flags = 0;
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sdmac->buf_tail = 0;
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sdmac->buf_tail = 0;
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+ sdmac->buf_ptail = 0;
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+ sdmac->chn_real_count = 0;
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dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
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dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
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sg_len, channel);
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sg_len, channel);
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@@ -1288,6 +1291,8 @@ static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
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sdmac->status = DMA_IN_PROGRESS;
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sdmac->status = DMA_IN_PROGRESS;
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sdmac->buf_tail = 0;
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sdmac->buf_tail = 0;
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+ sdmac->buf_ptail = 0;
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+ sdmac->chn_real_count = 0;
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sdmac->period_len = period_len;
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sdmac->period_len = period_len;
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sdmac->flags |= IMX_DMA_SG_LOOP;
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sdmac->flags |= IMX_DMA_SG_LOOP;
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@@ -1385,7 +1390,7 @@ static enum dma_status sdma_tx_status(struct dma_chan *chan,
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u32 residue;
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u32 residue;
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if (sdmac->flags & IMX_DMA_SG_LOOP)
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if (sdmac->flags & IMX_DMA_SG_LOOP)
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- residue = (sdmac->num_bd - sdmac->buf_tail) *
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+ residue = (sdmac->num_bd - sdmac->buf_ptail) *
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sdmac->period_len - sdmac->chn_real_count;
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sdmac->period_len - sdmac->chn_real_count;
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else
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else
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residue = sdmac->chn_count - sdmac->chn_real_count;
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residue = sdmac->chn_count - sdmac->chn_real_count;
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