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@@ -79,12 +79,17 @@ static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
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static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
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{
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- return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
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+ u16 version = le16_to_cpu(ah->eeprom.def.baseEepHeader.version);
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+
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+ return (version & AR5416_EEP_VER_MAJOR_MASK) >>
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+ AR5416_EEP_VER_MAJOR_SHIFT;
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}
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static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
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{
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- return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
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+ u16 version = le16_to_cpu(ah->eeprom.def.baseEepHeader.version);
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+
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+ return version & AR5416_EEP_VER_MINOR_MASK;
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}
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#define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
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@@ -130,10 +135,10 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
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static u32 ath9k_def_dump_modal_eeprom(char *buf, u32 len, u32 size,
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struct modal_eep_header *modal_hdr)
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{
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- PR_EEP("Chain0 Ant. Control", modal_hdr->antCtrlChain[0]);
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- PR_EEP("Chain1 Ant. Control", modal_hdr->antCtrlChain[1]);
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- PR_EEP("Chain2 Ant. Control", modal_hdr->antCtrlChain[2]);
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- PR_EEP("Ant. Common Control", modal_hdr->antCtrlCommon);
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+ PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
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+ PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
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+ PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
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+ PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
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PR_EEP("Chain0 Ant. Gain", modal_hdr->antennaGainCh[0]);
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PR_EEP("Chain1 Ant. Gain", modal_hdr->antennaGainCh[1]);
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PR_EEP("Chain2 Ant. Gain", modal_hdr->antennaGainCh[2]);
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@@ -189,9 +194,9 @@ static u32 ath9k_def_dump_modal_eeprom(char *buf, u32 len, u32 size,
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PR_EEP("Chain1 OutputBias", modal_hdr->ob_ch1);
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PR_EEP("Chain1 DriverBias", modal_hdr->db_ch1);
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PR_EEP("LNA Control", modal_hdr->lna_ctl);
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- PR_EEP("XPA Bias Freq0", modal_hdr->xpaBiasLvlFreq[0]);
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- PR_EEP("XPA Bias Freq1", modal_hdr->xpaBiasLvlFreq[1]);
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- PR_EEP("XPA Bias Freq2", modal_hdr->xpaBiasLvlFreq[2]);
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+ PR_EEP("XPA Bias Freq0", le16_to_cpu(modal_hdr->xpaBiasLvlFreq[0]));
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+ PR_EEP("XPA Bias Freq1", le16_to_cpu(modal_hdr->xpaBiasLvlFreq[1]));
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+ PR_EEP("XPA Bias Freq2", le16_to_cpu(modal_hdr->xpaBiasLvlFreq[2]));
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return len;
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}
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@@ -201,6 +206,7 @@ static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
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{
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struct ar5416_eeprom_def *eep = &ah->eeprom.def;
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struct base_eep_header *pBase = &eep->baseEepHeader;
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+ u32 binBuildNumber = le32_to_cpu(pBase->binBuildNumber);
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if (!dump_base_hdr) {
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len += scnprintf(buf + len, size - len,
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@@ -214,12 +220,12 @@ static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
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goto out;
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}
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- PR_EEP("Major Version", pBase->version >> 12);
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- PR_EEP("Minor Version", pBase->version & 0xFFF);
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- PR_EEP("Checksum", pBase->checksum);
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- PR_EEP("Length", pBase->length);
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- PR_EEP("RegDomain1", pBase->regDmn[0]);
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- PR_EEP("RegDomain2", pBase->regDmn[1]);
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+ PR_EEP("Major Version", ath9k_hw_def_get_eeprom_ver(ah));
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+ PR_EEP("Minor Version", ath9k_hw_def_get_eeprom_rev(ah));
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+ PR_EEP("Checksum", le16_to_cpu(pBase->checksum));
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+ PR_EEP("Length", le16_to_cpu(pBase->length));
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+ PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
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+ PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
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PR_EEP("TX Mask", pBase->txMask);
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PR_EEP("RX Mask", pBase->rxMask);
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PR_EEP("Allow 5GHz", !!(pBase->opCapFlags & AR5416_OPFLAGS_11A));
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@@ -232,10 +238,10 @@ static u32 ath9k_hw_def_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
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AR5416_OPFLAGS_N_5G_HT20));
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PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags &
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AR5416_OPFLAGS_N_5G_HT40));
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- PR_EEP("Big Endian", !!(pBase->eepMisc & 0x01));
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- PR_EEP("Cal Bin Major Ver", (pBase->binBuildNumber >> 24) & 0xFF);
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- PR_EEP("Cal Bin Minor Ver", (pBase->binBuildNumber >> 16) & 0xFF);
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- PR_EEP("Cal Bin Build", (pBase->binBuildNumber >> 8) & 0xFF);
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+ PR_EEP("Big Endian", !!(pBase->eepMisc & AR5416_EEPMISC_BIG_ENDIAN));
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+ PR_EEP("Cal Bin Major Ver", (binBuildNumber >> 24) & 0xFF);
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+ PR_EEP("Cal Bin Minor Ver", (binBuildNumber >> 16) & 0xFF);
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+ PR_EEP("Cal Bin Build", (binBuildNumber >> 8) & 0xFF);
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PR_EEP("OpenLoop Power Ctrl", pBase->openLoopPwrCntl);
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len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
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@@ -268,61 +274,40 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
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return err;
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if (need_swap)
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- el = swab16(eep->baseEepHeader.length);
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+ el = swab16((__force u16)eep->baseEepHeader.length);
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else
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- el = eep->baseEepHeader.length;
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+ el = le16_to_cpu(eep->baseEepHeader.length);
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el = min(el / sizeof(u16), SIZE_EEPROM_DEF);
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if (!ath9k_hw_nvram_validate_checksum(ah, el))
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return -EINVAL;
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if (need_swap) {
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- u32 integer, j;
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- u16 word;
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-
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- word = swab16(eep->baseEepHeader.length);
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- eep->baseEepHeader.length = word;
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-
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- word = swab16(eep->baseEepHeader.checksum);
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- eep->baseEepHeader.checksum = word;
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-
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- word = swab16(eep->baseEepHeader.version);
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- eep->baseEepHeader.version = word;
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-
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- word = swab16(eep->baseEepHeader.regDmn[0]);
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- eep->baseEepHeader.regDmn[0] = word;
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-
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- word = swab16(eep->baseEepHeader.regDmn[1]);
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- eep->baseEepHeader.regDmn[1] = word;
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-
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- word = swab16(eep->baseEepHeader.rfSilent);
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- eep->baseEepHeader.rfSilent = word;
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-
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- word = swab16(eep->baseEepHeader.blueToothOptions);
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- eep->baseEepHeader.blueToothOptions = word;
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+ u32 j;
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- word = swab16(eep->baseEepHeader.deviceCap);
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- eep->baseEepHeader.deviceCap = word;
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+ EEPROM_FIELD_SWAB16(eep->baseEepHeader.length);
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+ EEPROM_FIELD_SWAB16(eep->baseEepHeader.checksum);
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+ EEPROM_FIELD_SWAB16(eep->baseEepHeader.version);
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+ EEPROM_FIELD_SWAB16(eep->baseEepHeader.regDmn[0]);
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+ EEPROM_FIELD_SWAB16(eep->baseEepHeader.regDmn[1]);
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+ EEPROM_FIELD_SWAB16(eep->baseEepHeader.rfSilent);
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+ EEPROM_FIELD_SWAB16(eep->baseEepHeader.blueToothOptions);
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+ EEPROM_FIELD_SWAB16(eep->baseEepHeader.deviceCap);
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for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
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struct modal_eep_header *pModal =
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&eep->modalHeader[j];
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- integer = swab32(pModal->antCtrlCommon);
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- pModal->antCtrlCommon = integer;
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+ EEPROM_FIELD_SWAB32(pModal->antCtrlCommon);
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- for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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- integer = swab32(pModal->antCtrlChain[i]);
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- pModal->antCtrlChain[i] = integer;
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- }
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- for (i = 0; i < 3; i++) {
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- word = swab16(pModal->xpaBiasLvlFreq[i]);
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- pModal->xpaBiasLvlFreq[i] = word;
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- }
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+ for (i = 0; i < AR5416_MAX_CHAINS; i++)
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+ EEPROM_FIELD_SWAB32(pModal->antCtrlChain[i]);
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- for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
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- word = swab16(pModal->spurChans[i].spurChan);
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- pModal->spurChans[i].spurChan = word;
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- }
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+ for (i = 0; i < 3; i++)
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+ EEPROM_FIELD_SWAB16(pModal->xpaBiasLvlFreq[i]);
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+
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+ for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++)
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+ EEPROM_FIELD_SWAB16(
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+ pModal->spurChans[i].spurChan);
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}
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}
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@@ -332,7 +317,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
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/* Enable fixup for AR_AN_TOP2 if necessary */
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if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
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- ((eep->baseEepHeader.version & 0xff) > 0x0a) &&
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+ ((le16_to_cpu(eep->baseEepHeader.version) & 0xff) > 0x0a) &&
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(eep->baseEepHeader.pwdclkind == 0))
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ah->need_an_top2_fixup = true;
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@@ -365,13 +350,13 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
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case EEP_MAC_MSW:
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return get_unaligned_be16(pBase->macAddr + 4);
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case EEP_REG_0:
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- return pBase->regDmn[0];
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+ return le16_to_cpu(pBase->regDmn[0]);
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case EEP_OP_CAP:
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- return pBase->deviceCap;
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+ return le16_to_cpu(pBase->deviceCap);
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case EEP_OP_MODE:
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return pBase->opCapFlags;
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case EEP_RF_SILENT:
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- return pBase->rfSilent;
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+ return le16_to_cpu(pBase->rfSilent);
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case EEP_OB_5:
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return pModal[0].ob;
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case EEP_DB_5:
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@@ -380,8 +365,6 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
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return pModal[1].ob;
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case EEP_DB_2:
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return pModal[1].db;
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- case EEP_MINOR_REV:
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- return AR5416_VER_MASK;
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case EEP_TX_MASK:
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return pBase->txMask;
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case EEP_RX_MASK:
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@@ -393,27 +376,27 @@ static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
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case EEP_TXGAIN_TYPE:
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return pBase->txGainType;
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case EEP_OL_PWRCTRL:
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- if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
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+ if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_19)
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return pBase->openLoopPwrCntl ? true : false;
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else
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return false;
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case EEP_RC_CHAIN_MASK:
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- if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
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+ if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_19)
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return pBase->rcChainMask;
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else
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return 0;
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case EEP_DAC_HPWR_5G:
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- if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
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+ if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_20)
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return pBase->dacHiPwrMode_5G;
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else
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return 0;
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case EEP_FRAC_N_5G:
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- if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
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+ if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_22)
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return pBase->frac_n_5g;
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else
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return 0;
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case EEP_PWR_TABLE_OFFSET:
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- if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
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+ if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_21)
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return pBase->pwr_table_offset;
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else
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return AR5416_PWR_TABLE_OFFSET_DB;
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@@ -436,7 +419,7 @@ static void ath9k_hw_def_set_gain(struct ath_hw *ah,
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u8 txRxAttenLocal, int regChainOffset, int i)
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{
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ENABLE_REG_RMW_BUFFER(ah);
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- if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
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+ if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_3) {
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txRxAttenLocal = pModal->txRxAttenCh[i];
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if (AR_SREV_9280_20_OR_LATER(ah)) {
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@@ -487,11 +470,13 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
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struct ar5416_eeprom_def *eep = &ah->eeprom.def;
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int i, regChainOffset;
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u8 txRxAttenLocal;
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+ u32 antCtrlCommon;
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pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
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txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
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+ antCtrlCommon = le32_to_cpu(pModal->antCtrlCommon);
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- REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
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+ REG_WRITE(ah, AR_PHY_SWITCH_COM, antCtrlCommon & 0xffff);
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for (i = 0; i < AR5416_MAX_CHAINS; i++) {
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if (AR_SREV_9280(ah)) {
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@@ -505,7 +490,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
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regChainOffset = i * 0x1000;
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REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
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- pModal->antCtrlChain[i]);
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+ le32_to_cpu(pModal->antCtrlChain[i]));
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REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
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(REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
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@@ -605,7 +590,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
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pModal->thresh62);
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}
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- if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
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+ if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_2) {
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REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
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AR_PHY_TX_END_DATA_START,
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pModal->txFrameToDataStart);
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@@ -613,7 +598,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
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pModal->txFrameToPaOn);
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}
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- if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
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+ if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_3) {
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if (IS_CHAN_HT40(chan))
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REG_RMW_FIELD(ah, AR_PHY_SETTLING,
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AR_PHY_SETTLING_SWITCH,
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@@ -621,13 +606,14 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
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}
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if (AR_SREV_9280_20_OR_LATER(ah) &&
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- AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
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+ ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_19)
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REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
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AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
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pModal->miscBits);
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- if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
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+ if (AR_SREV_9280_20(ah) &&
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+ ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_20) {
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if (IS_CHAN_2GHZ(chan))
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REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
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eep->baseEepHeader.dacLpMode);
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@@ -651,7 +637,7 @@ static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
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static void ath9k_hw_def_set_addac(struct ath_hw *ah,
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struct ath9k_channel *chan)
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{
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-#define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
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+#define XPA_LVL_FREQ(cnt) (le16_to_cpu(pModal->xpaBiasLvlFreq[cnt]))
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struct modal_eep_header *pModal;
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struct ar5416_eeprom_def *eep = &ah->eeprom.def;
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u8 biaslevel;
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@@ -798,8 +784,7 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
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pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
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- if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
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- AR5416_EEP_MINOR_VER_2) {
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+ if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_2) {
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pdGainOverlap_t2 =
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pEepData->modalHeader[modalIdx].pdGainOverlap;
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} else {
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@@ -1171,10 +1156,8 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
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memset(ratesArray, 0, sizeof(ratesArray));
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- if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
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- AR5416_EEP_MINOR_VER_2) {
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+ if (ath9k_hw_def_get_eeprom_rev(ah) >= AR5416_EEP_MINOR_VER_2)
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ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
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- }
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ath9k_hw_set_def_power_per_rate_table(ah, chan,
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&ratesArray[0], cfgCtl,
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@@ -1314,7 +1297,14 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
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static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
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{
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- return ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan;
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+ __le16 spch = ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan;
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+
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+ return le16_to_cpu(spch);
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+}
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+
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+static u8 ath9k_hw_def_get_eepmisc(struct ath_hw *ah)
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+{
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+ return ah->eeprom.def.baseEepHeader.eepMisc;
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}
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const struct eeprom_ops eep_def_ops = {
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@@ -1327,5 +1317,6 @@ const struct eeprom_ops eep_def_ops = {
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.set_board_values = ath9k_hw_def_set_board_values,
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.set_addac = ath9k_hw_def_set_addac,
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.set_txpower = ath9k_hw_def_set_txpower,
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- .get_spur_channel = ath9k_hw_def_get_spur_channel
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+ .get_spur_channel = ath9k_hw_def_get_spur_channel,
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+ .get_eepmisc = ath9k_hw_def_get_eepmisc
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};
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