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@@ -5284,15 +5284,14 @@ static unsigned int mvpp2_tx_done(struct mvpp2_port *port, u32 cause,
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/* Allocate and initialize descriptors for aggr TXQ */
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static int mvpp2_aggr_txq_init(struct platform_device *pdev,
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- struct mvpp2_tx_queue *aggr_txq,
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- int desc_num, int cpu,
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+ struct mvpp2_tx_queue *aggr_txq, int cpu,
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struct mvpp2 *priv)
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{
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u32 txq_dma;
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/* Allocate memory for TX descriptors */
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aggr_txq->descs = dma_alloc_coherent(&pdev->dev,
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- desc_num * MVPP2_DESC_ALIGNED_SIZE,
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+ MVPP2_AGGR_TXQ_SIZE * MVPP2_DESC_ALIGNED_SIZE,
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&aggr_txq->descs_dma, GFP_KERNEL);
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if (!aggr_txq->descs)
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return -ENOMEM;
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@@ -5313,7 +5312,8 @@ static int mvpp2_aggr_txq_init(struct platform_device *pdev,
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MVPP22_AGGR_TXQ_DESC_ADDR_OFFS;
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mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu), txq_dma);
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- mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu), desc_num);
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+ mvpp2_write(priv, MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu),
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+ MVPP2_AGGR_TXQ_SIZE);
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return 0;
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}
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@@ -7445,8 +7445,7 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
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for_each_present_cpu(i) {
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priv->aggr_txqs[i].id = i;
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priv->aggr_txqs[i].size = MVPP2_AGGR_TXQ_SIZE;
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- err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i],
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- MVPP2_AGGR_TXQ_SIZE, i, priv);
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+ err = mvpp2_aggr_txq_init(pdev, &priv->aggr_txqs[i], i, priv);
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if (err < 0)
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return err;
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}
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