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@@ -67,7 +67,7 @@
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#define RALINK_PCIE2_CLK_EN BIT(26)
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#define RALINK_PCIE2_CLK_EN BIT(26)
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#define RALINK_PCI_CONFIG_ADDR 0x20
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#define RALINK_PCI_CONFIG_ADDR 0x20
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-#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
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+#define RALINK_PCI_CONFIG_DATA 0x24
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#define RALINK_PCI_MEMBASE 0x28
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#define RALINK_PCI_MEMBASE 0x28
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#define RALINK_PCI_IOBASE 0x2C
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#define RALINK_PCI_IOBASE 0x2C
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#define RALINK_PCIE0_RST BIT(24)
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#define RALINK_PCIE0_RST BIT(24)
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@@ -187,7 +187,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
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writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
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writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
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- return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
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+ return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
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}
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}
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struct pci_ops mt7621_pci_ops = {
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struct pci_ops mt7621_pci_ops = {
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@@ -202,7 +202,7 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
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u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
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u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
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- return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
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+ return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
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}
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}
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static void
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static void
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@@ -211,7 +211,7 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
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u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
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u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
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pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
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- pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
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+ pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
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}
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}
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int
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int
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