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@@ -0,0 +1,455 @@
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+/*
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+ * TI TPS68470 PMIC operation region driver
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+ *
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+ * Copyright (C) 2017 Intel Corporation. All rights reserved.
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+ *
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+ * Author: Rajmohan Mani <rajmohan.mani@intel.com>
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License version
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+ * 2 as published by the Free Software Foundation.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * Based on drivers/acpi/pmic/intel_pmic* drivers
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+ */
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+
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+#include <linux/acpi.h>
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+#include <linux/mfd/tps68470.h>
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+#include <linux/init.h>
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+#include <linux/platform_device.h>
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+#include <linux/regmap.h>
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+
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+struct tps68470_pmic_table {
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+ u32 address; /* operation region address */
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+ u32 reg; /* corresponding register */
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+ u32 bitmask; /* bit mask for power, clock */
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+};
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+
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+#define TI_PMIC_POWER_OPREGION_ID 0xB0
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+#define TI_PMIC_VR_VAL_OPREGION_ID 0xB1
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+#define TI_PMIC_CLOCK_OPREGION_ID 0xB2
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+#define TI_PMIC_CLKFREQ_OPREGION_ID 0xB3
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+
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+struct tps68470_pmic_opregion {
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+ struct mutex lock;
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+ struct regmap *regmap;
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+};
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+
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+#define S_IO_I2C_EN (BIT(0) | BIT(1))
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+
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+static const struct tps68470_pmic_table power_table[] = {
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+ {
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+ .address = 0x00,
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+ .reg = TPS68470_REG_S_I2C_CTL,
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+ .bitmask = S_IO_I2C_EN,
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+ /* S_I2C_CTL */
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+ },
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+ {
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+ .address = 0x04,
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+ .reg = TPS68470_REG_VCMCTL,
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+ .bitmask = BIT(0),
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+ /* VCMCTL */
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+ },
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+ {
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+ .address = 0x08,
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+ .reg = TPS68470_REG_VAUX1CTL,
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+ .bitmask = BIT(0),
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+ /* VAUX1_CTL */
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+ },
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+ {
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+ .address = 0x0C,
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+ .reg = TPS68470_REG_VAUX2CTL,
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+ .bitmask = BIT(0),
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+ /* VAUX2CTL */
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+ },
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+ {
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+ .address = 0x10,
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+ .reg = TPS68470_REG_VACTL,
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+ .bitmask = BIT(0),
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+ /* VACTL */
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+ },
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+ {
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+ .address = 0x14,
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+ .reg = TPS68470_REG_VDCTL,
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+ .bitmask = BIT(0),
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+ /* VDCTL */
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+ },
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+};
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+
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+/* Table to set voltage regulator value */
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+static const struct tps68470_pmic_table vr_val_table[] = {
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+ {
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+ .address = 0x00,
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+ .reg = TPS68470_REG_VSIOVAL,
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+ .bitmask = TPS68470_VSIOVAL_IOVOLT_MASK,
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+ /* TPS68470_REG_VSIOVAL */
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+ },
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+ {
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+ .address = 0x04,
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+ .reg = TPS68470_REG_VIOVAL,
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+ .bitmask = TPS68470_VIOVAL_IOVOLT_MASK,
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+ /* TPS68470_REG_VIOVAL */
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+ },
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+ {
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+ .address = 0x08,
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+ .reg = TPS68470_REG_VCMVAL,
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+ .bitmask = TPS68470_VCMVAL_VCVOLT_MASK,
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+ /* TPS68470_REG_VCMVAL */
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+ },
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+ {
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+ .address = 0x0C,
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+ .reg = TPS68470_REG_VAUX1VAL,
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+ .bitmask = TPS68470_VAUX1VAL_AUX1VOLT_MASK,
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+ /* TPS68470_REG_VAUX1VAL */
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+ },
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+ {
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+ .address = 0x10,
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+ .reg = TPS68470_REG_VAUX2VAL,
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+ .bitmask = TPS68470_VAUX2VAL_AUX2VOLT_MASK,
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+ /* TPS68470_REG_VAUX2VAL */
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+ },
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+ {
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+ .address = 0x14,
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+ .reg = TPS68470_REG_VAVAL,
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+ .bitmask = TPS68470_VAVAL_AVOLT_MASK,
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+ /* TPS68470_REG_VAVAL */
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+ },
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+ {
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+ .address = 0x18,
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+ .reg = TPS68470_REG_VDVAL,
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+ .bitmask = TPS68470_VDVAL_DVOLT_MASK,
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+ /* TPS68470_REG_VDVAL */
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+ },
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+};
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+
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+/* Table to configure clock frequency */
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+static const struct tps68470_pmic_table clk_freq_table[] = {
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+ {
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+ .address = 0x00,
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+ .reg = TPS68470_REG_POSTDIV2,
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+ .bitmask = BIT(0) | BIT(1),
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+ /* TPS68470_REG_POSTDIV2 */
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+ },
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+ {
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+ .address = 0x04,
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+ .reg = TPS68470_REG_BOOSTDIV,
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+ .bitmask = 0x1F,
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+ /* TPS68470_REG_BOOSTDIV */
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+ },
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+ {
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+ .address = 0x08,
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+ .reg = TPS68470_REG_BUCKDIV,
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+ .bitmask = 0x0F,
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+ /* TPS68470_REG_BUCKDIV */
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+ },
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+ {
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+ .address = 0x0C,
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+ .reg = TPS68470_REG_PLLSWR,
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+ .bitmask = 0x13,
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+ /* TPS68470_REG_PLLSWR */
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+ },
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+ {
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+ .address = 0x10,
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+ .reg = TPS68470_REG_XTALDIV,
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+ .bitmask = 0xFF,
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+ /* TPS68470_REG_XTALDIV */
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+ },
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+ {
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+ .address = 0x14,
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+ .reg = TPS68470_REG_PLLDIV,
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+ .bitmask = 0xFF,
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+ /* TPS68470_REG_PLLDIV */
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+ },
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+ {
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+ .address = 0x18,
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+ .reg = TPS68470_REG_POSTDIV,
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+ .bitmask = 0x83,
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+ /* TPS68470_REG_POSTDIV */
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+ },
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+};
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+
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+/* Table to configure and enable clocks */
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+static const struct tps68470_pmic_table clk_table[] = {
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+ {
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+ .address = 0x00,
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+ .reg = TPS68470_REG_PLLCTL,
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+ .bitmask = 0xF5,
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+ /* TPS68470_REG_PLLCTL */
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+ },
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+ {
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+ .address = 0x04,
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+ .reg = TPS68470_REG_PLLCTL2,
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+ .bitmask = BIT(0),
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+ /* TPS68470_REG_PLLCTL2 */
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+ },
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+ {
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+ .address = 0x08,
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+ .reg = TPS68470_REG_CLKCFG1,
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+ .bitmask = TPS68470_CLKCFG1_MODE_A_MASK |
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+ TPS68470_CLKCFG1_MODE_B_MASK,
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+ /* TPS68470_REG_CLKCFG1 */
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+ },
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+ {
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+ .address = 0x0C,
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+ .reg = TPS68470_REG_CLKCFG2,
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+ .bitmask = TPS68470_CLKCFG1_MODE_A_MASK |
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+ TPS68470_CLKCFG1_MODE_B_MASK,
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+ /* TPS68470_REG_CLKCFG2 */
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+ },
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+};
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+
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+static int pmic_get_reg_bit(u64 address,
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+ const struct tps68470_pmic_table *table,
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+ const unsigned int table_size, int *reg,
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+ int *bitmask)
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+{
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+ u64 i;
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+
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+ i = address / 4;
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+ if (i >= table_size)
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+ return -ENOENT;
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+
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+ if (!reg || !bitmask)
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+ return -EINVAL;
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+
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+ *reg = table[i].reg;
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+ *bitmask = table[i].bitmask;
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+
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+ return 0;
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+}
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+
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+static int tps68470_pmic_get_power(struct regmap *regmap, int reg,
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+ int bitmask, u64 *value)
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+{
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+ unsigned int data;
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+
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+ if (regmap_read(regmap, reg, &data))
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+ return -EIO;
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+
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+ *value = (data & bitmask) ? 1 : 0;
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+ return 0;
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+}
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+
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+static int tps68470_pmic_get_vr_val(struct regmap *regmap, int reg,
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+ int bitmask, u64 *value)
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+{
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+ unsigned int data;
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+
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+ if (regmap_read(regmap, reg, &data))
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+ return -EIO;
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+
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+ *value = data & bitmask;
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+ return 0;
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+}
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+
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+static int tps68470_pmic_get_clk(struct regmap *regmap, int reg,
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+ int bitmask, u64 *value)
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+{
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+ unsigned int data;
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+
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+ if (regmap_read(regmap, reg, &data))
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+ return -EIO;
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+
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+ *value = (data & bitmask) ? 1 : 0;
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+ return 0;
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+}
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+
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+static int tps68470_pmic_get_clk_freq(struct regmap *regmap, int reg,
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+ int bitmask, u64 *value)
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+{
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+ unsigned int data;
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+
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+ if (regmap_read(regmap, reg, &data))
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+ return -EIO;
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+
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+ *value = data & bitmask;
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+ return 0;
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+}
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+
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+static int ti_tps68470_regmap_update_bits(struct regmap *regmap, int reg,
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+ int bitmask, u64 value)
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+{
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+ return regmap_update_bits(regmap, reg, bitmask, value);
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+}
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+
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+static acpi_status tps68470_pmic_common_handler(u32 function,
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+ acpi_physical_address address,
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+ u32 bits, u64 *value,
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+ void *region_context,
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+ int (*get)(struct regmap *,
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+ int, int, u64 *),
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+ int (*update)(struct regmap *,
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+ int, int, u64),
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+ const struct tps68470_pmic_table *tbl,
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+ unsigned int tbl_size)
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+{
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+ struct tps68470_pmic_opregion *opregion = region_context;
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+ struct regmap *regmap = opregion->regmap;
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+ int reg, ret, bitmask;
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+
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+ if (bits != 32)
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+ return AE_BAD_PARAMETER;
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+
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+ ret = pmic_get_reg_bit(address, tbl, tbl_size, ®, &bitmask);
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+ if (ret < 0)
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+ return AE_BAD_PARAMETER;
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+
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+ if (function == ACPI_WRITE && *value > bitmask)
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+ return AE_BAD_PARAMETER;
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+
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+ mutex_lock(&opregion->lock);
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+
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+ ret = (function == ACPI_READ) ?
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+ get(regmap, reg, bitmask, value) :
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+ update(regmap, reg, bitmask, *value);
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+
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+ mutex_unlock(&opregion->lock);
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+
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+ return ret ? AE_ERROR : AE_OK;
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+}
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+
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+static acpi_status tps68470_pmic_cfreq_handler(u32 function,
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+ acpi_physical_address address,
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+ u32 bits, u64 *value,
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+ void *handler_context,
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+ void *region_context)
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+{
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+ return tps68470_pmic_common_handler(function, address, bits, value,
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+ region_context,
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+ tps68470_pmic_get_clk_freq,
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+ ti_tps68470_regmap_update_bits,
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+ clk_freq_table,
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+ ARRAY_SIZE(clk_freq_table));
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+}
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+
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+static acpi_status tps68470_pmic_clk_handler(u32 function,
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+ acpi_physical_address address, u32 bits,
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+ u64 *value, void *handler_context,
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+ void *region_context)
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+{
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+ return tps68470_pmic_common_handler(function, address, bits, value,
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+ region_context,
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+ tps68470_pmic_get_clk,
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+ ti_tps68470_regmap_update_bits,
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+ clk_table,
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+ ARRAY_SIZE(clk_table));
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+}
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+
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+static acpi_status tps68470_pmic_vrval_handler(u32 function,
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+ acpi_physical_address address,
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+ u32 bits, u64 *value,
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+ void *handler_context,
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+ void *region_context)
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+{
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+ return tps68470_pmic_common_handler(function, address, bits, value,
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+ region_context,
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+ tps68470_pmic_get_vr_val,
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+ ti_tps68470_regmap_update_bits,
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+ vr_val_table,
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+ ARRAY_SIZE(vr_val_table));
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+}
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+
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+static acpi_status tps68470_pmic_pwr_handler(u32 function,
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+ acpi_physical_address address,
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+ u32 bits, u64 *value,
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+ void *handler_context,
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+ void *region_context)
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+{
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+ if (bits != 32)
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+ return AE_BAD_PARAMETER;
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+
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+ /* set/clear for bit 0, bits 0 and 1 together */
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+ if (function == ACPI_WRITE &&
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+ !(*value == 0 || *value == 1 || *value == 3)) {
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+ return AE_BAD_PARAMETER;
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+ }
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+
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+ return tps68470_pmic_common_handler(function, address, bits, value,
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+ region_context,
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+ tps68470_pmic_get_power,
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+ ti_tps68470_regmap_update_bits,
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+ power_table,
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+ ARRAY_SIZE(power_table));
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+}
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+
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+static int tps68470_pmic_opregion_probe(struct platform_device *pdev)
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+{
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+ struct regmap *tps68470_regmap = dev_get_drvdata(pdev->dev.parent);
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+ acpi_handle handle = ACPI_HANDLE(pdev->dev.parent);
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+ struct device *dev = &pdev->dev;
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+ struct tps68470_pmic_opregion *opregion;
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+ acpi_status status;
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+
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+ if (!dev || !tps68470_regmap) {
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+ dev_warn(dev, "dev or regmap is NULL\n");
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+ return -EINVAL;
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+ }
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+
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+ if (!handle) {
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+ dev_warn(dev, "acpi handle is NULL\n");
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+ return -ENODEV;
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+ }
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+
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+ opregion = devm_kzalloc(dev, sizeof(*opregion), GFP_KERNEL);
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+ if (!opregion)
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+ return -ENOMEM;
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+
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+ mutex_init(&opregion->lock);
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+ opregion->regmap = tps68470_regmap;
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+
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+ status = acpi_install_address_space_handler(handle,
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+ TI_PMIC_POWER_OPREGION_ID,
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+ tps68470_pmic_pwr_handler,
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+ NULL, opregion);
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+ if (ACPI_FAILURE(status))
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+ goto out_mutex_destroy;
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+
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+ status = acpi_install_address_space_handler(handle,
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+ TI_PMIC_VR_VAL_OPREGION_ID,
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+ tps68470_pmic_vrval_handler,
|
|
|
+ NULL, opregion);
|
|
|
+ if (ACPI_FAILURE(status))
|
|
|
+ goto out_remove_power_handler;
|
|
|
+
|
|
|
+ status = acpi_install_address_space_handler(handle,
|
|
|
+ TI_PMIC_CLOCK_OPREGION_ID,
|
|
|
+ tps68470_pmic_clk_handler,
|
|
|
+ NULL, opregion);
|
|
|
+ if (ACPI_FAILURE(status))
|
|
|
+ goto out_remove_vr_val_handler;
|
|
|
+
|
|
|
+ status = acpi_install_address_space_handler(handle,
|
|
|
+ TI_PMIC_CLKFREQ_OPREGION_ID,
|
|
|
+ tps68470_pmic_cfreq_handler,
|
|
|
+ NULL, opregion);
|
|
|
+ if (ACPI_FAILURE(status))
|
|
|
+ goto out_remove_clk_handler;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+
|
|
|
+out_remove_clk_handler:
|
|
|
+ acpi_remove_address_space_handler(handle, TI_PMIC_CLOCK_OPREGION_ID,
|
|
|
+ tps68470_pmic_clk_handler);
|
|
|
+out_remove_vr_val_handler:
|
|
|
+ acpi_remove_address_space_handler(handle, TI_PMIC_VR_VAL_OPREGION_ID,
|
|
|
+ tps68470_pmic_vrval_handler);
|
|
|
+out_remove_power_handler:
|
|
|
+ acpi_remove_address_space_handler(handle, TI_PMIC_POWER_OPREGION_ID,
|
|
|
+ tps68470_pmic_pwr_handler);
|
|
|
+out_mutex_destroy:
|
|
|
+ mutex_destroy(&opregion->lock);
|
|
|
+ return -ENODEV;
|
|
|
+}
|
|
|
+
|
|
|
+static struct platform_driver tps68470_pmic_opregion_driver = {
|
|
|
+ .probe = tps68470_pmic_opregion_probe,
|
|
|
+ .driver = {
|
|
|
+ .name = "tps68470_pmic_opregion",
|
|
|
+ },
|
|
|
+};
|
|
|
+
|
|
|
+builtin_platform_driver(tps68470_pmic_opregion_driver)
|
Rafael J. Wysocki