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@@ -33,6 +33,8 @@
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/* PEX Internal Configuration Registers */
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#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
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+#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
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+#define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */
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#define PCIE_IATU_NUM 6
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@@ -124,6 +126,14 @@ static int ls_pcie_link_up(struct dw_pcie *pci)
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return 1;
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}
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+/* Forward error response of outbound non-posted requests */
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+static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
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+{
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+ struct dw_pcie *pci = pcie->pci;
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+
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+ iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR);
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+}
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+
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static int ls_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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@@ -135,6 +145,7 @@ static int ls_pcie_host_init(struct pcie_port *pp)
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* dw_pcie_setup_rc() will reconfigure the outbound windows.
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*/
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ls_pcie_disable_outbound_atus(pcie);
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+ ls_pcie_fix_error_response(pcie);
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dw_pcie_dbi_ro_wr_en(pci);
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ls_pcie_clear_multifunction(pcie);
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