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@@ -312,6 +312,14 @@ enum arm_smmu_implementation {
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CAVIUM_SMMUV2,
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};
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+/* Until ACPICA headers cover IORT rev. C */
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+#ifndef ACPI_IORT_SMMU_CORELINK_MMU401
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+#define ACPI_IORT_SMMU_CORELINK_MMU401 0x4
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+#endif
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+#ifndef ACPI_IORT_SMMU_CAVIUM_THUNDERX
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+#define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x5
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+#endif
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+
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struct arm_smmu_s2cr {
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struct iommu_group *group;
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int count;
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@@ -2073,6 +2081,10 @@ static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu)
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smmu->version = ARM_SMMU_V1;
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smmu->model = GENERIC_SMMU;
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break;
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+ case ACPI_IORT_SMMU_CORELINK_MMU401:
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+ smmu->version = ARM_SMMU_V1_64K;
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+ smmu->model = GENERIC_SMMU;
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+ break;
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case ACPI_IORT_SMMU_V2:
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smmu->version = ARM_SMMU_V2;
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smmu->model = GENERIC_SMMU;
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@@ -2081,6 +2093,10 @@ static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu)
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smmu->version = ARM_SMMU_V2;
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smmu->model = ARM_MMU500;
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break;
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+ case ACPI_IORT_SMMU_CAVIUM_THUNDERX:
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+ smmu->version = ARM_SMMU_V2;
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+ smmu->model = CAVIUM_SMMUV2;
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+ break;
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default:
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ret = -ENODEV;
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}
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