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@@ -48,6 +48,7 @@ MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
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MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
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MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
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MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
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+MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
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#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
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#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
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@@ -221,6 +222,7 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
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ARRAY_SIZE(golden_settings_sdma1_4_2));
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break;
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case CHIP_RAVEN:
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+ case CHIP_PICASSO:
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soc15_program_register_sequence(adev,
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golden_settings_sdma_4_1,
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ARRAY_SIZE(golden_settings_sdma_4_1));
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@@ -269,6 +271,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
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case CHIP_RAVEN:
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chip_name = "raven";
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break;
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+ case CHIP_PICASSO:
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+ chip_name = "picasso";
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+ break;
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default:
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BUG();
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}
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@@ -849,6 +854,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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+ case CHIP_PICASSO:
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sdma_v4_1_init_power_gating(adev);
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sdma_v4_1_update_power_gating(adev, true);
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break;
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@@ -1256,7 +1262,7 @@ static int sdma_v4_0_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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- if (adev->asic_type == CHIP_RAVEN)
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+ if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO)
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adev->sdma.num_instances = 1;
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else
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adev->sdma.num_instances = 2;
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@@ -1599,6 +1605,7 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
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case CHIP_VEGA12:
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case CHIP_VEGA20:
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case CHIP_RAVEN:
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+ case CHIP_PICASSO:
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sdma_v4_0_update_medium_grain_clock_gating(adev,
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state == AMD_CG_STATE_GATE ? true : false);
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sdma_v4_0_update_medium_grain_light_sleep(adev,
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@@ -1617,6 +1624,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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+ case CHIP_PICASSO:
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sdma_v4_1_update_power_gating(adev,
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state == AMD_PG_STATE_GATE ? true : false);
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break;
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