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@@ -125,6 +125,21 @@ static const char *tegra_xusb_padctl_get_group_name(struct pinctrl_dev *pinctrl,
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return padctl->soc->pins[group].name;
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}
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+static int tegra_xusb_padctl_get_group_pins(struct pinctrl_dev *pinctrl,
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+ unsigned group,
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+ const unsigned **pins,
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+ unsigned *num_pins)
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+{
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+ /*
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+ * For the tegra-xusb pad controller groups are synonomous
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+ * with lanes/pins and there is always one lane/pin per group.
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+ */
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+ *pins = &pinctrl->desc->pins[group].number;
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+ *num_pins = 1;
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+
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+ return 0;
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+}
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+
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enum tegra_xusb_padctl_param {
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TEGRA_XUSB_PADCTL_IDDQ,
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};
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@@ -248,6 +263,7 @@ static int tegra_xusb_padctl_dt_node_to_map(struct pinctrl_dev *pinctrl,
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static const struct pinctrl_ops tegra_xusb_padctl_pinctrl_ops = {
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.get_groups_count = tegra_xusb_padctl_get_groups_count,
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.get_group_name = tegra_xusb_padctl_get_group_name,
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+ .get_group_pins = tegra_xusb_padctl_get_group_pins,
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.dt_node_to_map = tegra_xusb_padctl_dt_node_to_map,
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.dt_free_map = pinctrl_utils_dt_free_map,
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};
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@@ -898,6 +914,8 @@ static int tegra_xusb_padctl_probe(struct platform_device *pdev)
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memset(&padctl->desc, 0, sizeof(padctl->desc));
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padctl->desc.name = dev_name(padctl->dev);
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+ padctl->desc.pins = tegra124_pins;
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+ padctl->desc.npins = ARRAY_SIZE(tegra124_pins);
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padctl->desc.pctlops = &tegra_xusb_padctl_pinctrl_ops;
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padctl->desc.pmxops = &tegra_xusb_padctl_pinmux_ops;
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padctl->desc.confops = &tegra_xusb_padctl_pinconf_ops;
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