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@@ -1,20 +1,8 @@
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+// SPDX-License-Identifier: GPL-2.0
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/*
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+ * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
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* Copyright Altera Corporation (C) 2014-2016. All rights reserved.
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* Copyright 2011-2012 Calxeda, Inc.
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- *
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- * This program is free software; you can redistribute it and/or modify it
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- * under the terms and conditions of the GNU General Public License,
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- * version 2, as published by the Free Software Foundation.
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- *
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- * This program is distributed in the hope it will be useful, but WITHOUT
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- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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- * more details.
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- *
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- * You should have received a copy of the GNU General Public License along with
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- * this program. If not, see <http://www.gnu.org/licenses/>.
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- *
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- * Adapted from the highbank_mc_edac driver.
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*/
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#include <asm/cacheflush.h>
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@@ -26,6 +14,7 @@
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#include <linux/irqchip/chained_irq.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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+#include <linux/notifier.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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@@ -80,6 +69,25 @@ static const struct altr_sdram_prv_data a10_data = {
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.ue_set_mask = A10_DIAGINT_TDERRA_MASK,
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};
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+static const struct altr_sdram_prv_data s10_data = {
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+ .ecc_ctrl_offset = S10_ECCCTRL1_OFST,
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+ .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
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+ .ecc_stat_offset = S10_INTSTAT_OFST,
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+ .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
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+ .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
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+ .ecc_saddr_offset = S10_SERRADDR_OFST,
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+ .ecc_daddr_offset = S10_DERRADDR_OFST,
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+ .ecc_irq_en_offset = S10_ERRINTEN_OFST,
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+ .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
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+ .ecc_irq_clr_offset = S10_INTSTAT_OFST,
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+ .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
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+ .ecc_cnt_rst_offset = S10_ECCCTRL1_OFST,
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+ .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
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+ .ce_ue_trgr_offset = S10_DIAGINTTEST_OFST,
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+ .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
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+ .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
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+};
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+
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/*********************** EDAC Memory Controller Functions ****************/
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/* The SDRAM controller uses the EDAC Memory Controller framework. */
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@@ -231,6 +239,7 @@ static unsigned long get_total_mem(void)
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static const struct of_device_id altr_sdram_ctrl_of_match[] = {
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{ .compatible = "altr,sdram-edac", .data = &c5_data},
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{ .compatible = "altr,sdram-edac-a10", .data = &a10_data},
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+ { .compatible = "altr,sdram-edac-s10", .data = &s10_data},
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{},
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};
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MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
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@@ -477,6 +486,292 @@ static int altr_sdram_remove(struct platform_device *pdev)
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return 0;
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}
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+/**************** Stratix 10 EDAC Memory Controller Functions ************/
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+
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+/**
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+ * s10_protected_reg_write
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+ * Write to a protected SMC register.
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+ * @context: Not used.
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+ * @reg: Address of register
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+ * @value: Value to write
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+ * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
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+ * INTEL_SIP_SMC_REG_ERROR on error
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+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
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+ */
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+static int s10_protected_reg_write(void *context, unsigned int reg,
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+ unsigned int val)
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+{
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+ struct arm_smccc_res result;
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+
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+ arm_smccc_smc(INTEL_SIP_SMC_REG_WRITE, reg, val, 0, 0,
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+ 0, 0, 0, &result);
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+
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+ return (int)result.a0;
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+}
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+
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+/**
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+ * s10_protected_reg_read
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+ * Read the status of a protected SMC register
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+ * @context: Not used.
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+ * @reg: Address of register
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+ * @value: Value read.
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+ * Return: INTEL_SIP_SMC_STATUS_OK (0) on success
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+ * INTEL_SIP_SMC_REG_ERROR on error
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+ * INTEL_SIP_SMC_RETURN_UNKNOWN_FUNCTION if not supported
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+ */
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+static int s10_protected_reg_read(void *context, unsigned int reg,
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+ unsigned int *val)
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+{
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+ struct arm_smccc_res result;
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+
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+ arm_smccc_smc(INTEL_SIP_SMC_REG_READ, reg, 0, 0, 0,
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+ 0, 0, 0, &result);
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+
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+ *val = (unsigned int)result.a1;
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+
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+ return (int)result.a0;
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+}
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+
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+static bool s10_sdram_writeable_reg(struct device *dev, unsigned int reg)
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+{
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+ switch (reg) {
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+ case S10_ECCCTRL1_OFST:
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+ case S10_ERRINTEN_OFST:
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+ case S10_INTMODE_OFST:
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+ case S10_INTSTAT_OFST:
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+ case S10_DIAGINTTEST_OFST:
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+ case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
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+ case S10_SYSMGR_ECC_INTMASK_SET_OFST:
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+ case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
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+ return true;
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+ }
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+ return false;
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+}
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+
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+static bool s10_sdram_readable_reg(struct device *dev, unsigned int reg)
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+{
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+ switch (reg) {
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+ case S10_ECCCTRL1_OFST:
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+ case S10_ERRINTEN_OFST:
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+ case S10_INTMODE_OFST:
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+ case S10_INTSTAT_OFST:
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+ case S10_DERRADDR_OFST:
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+ case S10_SERRADDR_OFST:
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+ case S10_DIAGINTTEST_OFST:
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+ case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
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+ case S10_SYSMGR_ECC_INTMASK_SET_OFST:
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+ case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
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+ case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
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+ case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
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+ return true;
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+ }
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+ return false;
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+}
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+
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+static bool s10_sdram_volatile_reg(struct device *dev, unsigned int reg)
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+{
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+ switch (reg) {
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+ case S10_ECCCTRL1_OFST:
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+ case S10_ERRINTEN_OFST:
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+ case S10_INTMODE_OFST:
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+ case S10_INTSTAT_OFST:
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+ case S10_DERRADDR_OFST:
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+ case S10_SERRADDR_OFST:
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+ case S10_DIAGINTTEST_OFST:
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+ case S10_SYSMGR_ECC_INTMASK_VAL_OFST:
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+ case S10_SYSMGR_ECC_INTMASK_SET_OFST:
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+ case S10_SYSMGR_ECC_INTMASK_CLR_OFST:
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+ case S10_SYSMGR_ECC_INTSTAT_SERR_OFST:
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+ case S10_SYSMGR_ECC_INTSTAT_DERR_OFST:
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+ return true;
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+ }
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+ return false;
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+}
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+
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+static const struct regmap_config s10_sdram_regmap_cfg = {
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+ .name = "s10_ddr",
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+ .reg_bits = 32,
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+ .reg_stride = 4,
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+ .val_bits = 32,
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+ .max_register = 0xffffffff,
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+ .writeable_reg = s10_sdram_writeable_reg,
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+ .readable_reg = s10_sdram_readable_reg,
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+ .volatile_reg = s10_sdram_volatile_reg,
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+ .reg_read = s10_protected_reg_read,
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+ .reg_write = s10_protected_reg_write,
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+ .use_single_rw = true,
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+};
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+
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+static int altr_s10_sdram_probe(struct platform_device *pdev)
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+{
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+ const struct of_device_id *id;
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+ struct edac_mc_layer layers[2];
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+ struct mem_ctl_info *mci;
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+ struct altr_sdram_mc_data *drvdata;
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+ const struct altr_sdram_prv_data *priv;
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+ struct regmap *regmap;
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+ struct dimm_info *dimm;
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+ u32 read_reg;
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+ int irq, ret = 0;
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+ unsigned long mem_size;
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+
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+ id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
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+ if (!id)
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+ return -ENODEV;
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+
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+ /* Grab specific offsets and masks for Stratix10 */
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+ priv = of_match_node(altr_sdram_ctrl_of_match,
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+ pdev->dev.of_node)->data;
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+
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+ regmap = devm_regmap_init(&pdev->dev, NULL, (void *)priv,
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+ &s10_sdram_regmap_cfg);
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+ if (IS_ERR(regmap))
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+ return PTR_ERR(regmap);
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+
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+ /* Validate the SDRAM controller has ECC enabled */
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+ if (regmap_read(regmap, priv->ecc_ctrl_offset, &read_reg) ||
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+ ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
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+ edac_printk(KERN_ERR, EDAC_MC,
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+ "No ECC/ECC disabled [0x%08X]\n", read_reg);
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+ return -ENODEV;
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+ }
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+
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+ /* Grab memory size from device tree. */
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+ mem_size = get_total_mem();
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+ if (!mem_size) {
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+ edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
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+ return -ENODEV;
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+ }
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+
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+ /* Ensure the SDRAM Interrupt is disabled */
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+ if (regmap_update_bits(regmap, priv->ecc_irq_en_offset,
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+ priv->ecc_irq_en_mask, 0)) {
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+ edac_printk(KERN_ERR, EDAC_MC,
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+ "Error disabling SDRAM ECC IRQ\n");
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+ return -ENODEV;
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+ }
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+
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+ /* Toggle to clear the SDRAM Error count */
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+ if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
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+ priv->ecc_cnt_rst_mask,
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+ priv->ecc_cnt_rst_mask)) {
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+ edac_printk(KERN_ERR, EDAC_MC,
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+ "Error clearing SDRAM ECC count\n");
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+ return -ENODEV;
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+ }
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+
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+ if (regmap_update_bits(regmap, priv->ecc_cnt_rst_offset,
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+ priv->ecc_cnt_rst_mask, 0)) {
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+ edac_printk(KERN_ERR, EDAC_MC,
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+ "Error clearing SDRAM ECC count\n");
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+ return -ENODEV;
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+ }
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+
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+ irq = platform_get_irq(pdev, 0);
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+ if (irq < 0) {
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+ edac_printk(KERN_ERR, EDAC_MC,
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+ "No irq %d in DT\n", irq);
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+ return -ENODEV;
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+ }
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+
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+ layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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+ layers[0].size = 1;
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+ layers[0].is_virt_csrow = true;
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+ layers[1].type = EDAC_MC_LAYER_CHANNEL;
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+ layers[1].size = 1;
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+ layers[1].is_virt_csrow = false;
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+ mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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+ sizeof(struct altr_sdram_mc_data));
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+ if (!mci)
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+ return -ENOMEM;
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+
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+ mci->pdev = &pdev->dev;
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+ drvdata = mci->pvt_info;
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+ drvdata->mc_vbase = regmap;
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+ drvdata->data = priv;
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+ platform_set_drvdata(pdev, mci);
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+
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+ if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
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+ edac_printk(KERN_ERR, EDAC_MC,
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+ "Unable to get managed device resource\n");
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+ ret = -ENOMEM;
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+ goto free;
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+ }
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+
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+ mci->mtype_cap = MEM_FLAG_DDR3;
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+ mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
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+ mci->edac_cap = EDAC_FLAG_SECDED;
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+ mci->mod_name = EDAC_MOD_STR;
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+ mci->ctl_name = dev_name(&pdev->dev);
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+ mci->scrub_mode = SCRUB_SW_SRC;
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+ mci->dev_name = dev_name(&pdev->dev);
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+
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+ dimm = *mci->dimms;
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+ dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
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+ dimm->grain = 8;
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+ dimm->dtype = DEV_X8;
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+ dimm->mtype = MEM_DDR3;
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+ dimm->edac_mode = EDAC_SECDED;
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+
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+ ret = edac_mc_add_mc(mci);
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+ if (ret < 0)
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+ goto err;
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+
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+ ret = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
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+ IRQF_SHARED, dev_name(&pdev->dev), mci);
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+ if (ret < 0) {
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+ edac_mc_printk(mci, KERN_ERR,
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+ "Unable to request irq %d\n", irq);
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+ ret = -ENODEV;
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+ goto err2;
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+ }
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+
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+ if (regmap_write(regmap, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
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+ S10_DDR0_IRQ_MASK)) {
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+ edac_printk(KERN_ERR, EDAC_MC,
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+ "Error clearing SDRAM ECC count\n");
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+ return -ENODEV;
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+ }
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+
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+ if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
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+ priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
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+ edac_mc_printk(mci, KERN_ERR,
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+ "Error enabling SDRAM ECC IRQ\n");
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+ ret = -ENODEV;
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+ goto err2;
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+ }
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+
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+ altr_sdr_mc_create_debugfs_nodes(mci);
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+
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+ devres_close_group(&pdev->dev, NULL);
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+
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+ return 0;
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+
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+err2:
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+ edac_mc_del_mc(&pdev->dev);
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+err:
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+ devres_release_group(&pdev->dev, NULL);
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+free:
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+ edac_mc_free(mci);
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+ edac_printk(KERN_ERR, EDAC_MC,
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+ "EDAC Probe Failed; Error %d\n", ret);
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+
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+ return ret;
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+}
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+
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+static int altr_s10_sdram_remove(struct platform_device *pdev)
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+{
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+ struct mem_ctl_info *mci = platform_get_drvdata(pdev);
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+
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+ edac_mc_del_mc(&pdev->dev);
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+ edac_mc_free(mci);
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+ platform_set_drvdata(pdev, NULL);
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+
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+ return 0;
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+}
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+
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+/************** </Stratix10 EDAC Memory Controller Functions> ***********/
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+
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/*
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|
|
* If you want to suspend, need to disable EDAC by removing it
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* from the device tree or defconfig.
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|
|
@@ -508,6 +803,20 @@ static struct platform_driver altr_sdram_edac_driver = {
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module_platform_driver(altr_sdram_edac_driver);
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+static struct platform_driver altr_s10_sdram_edac_driver = {
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+ .probe = altr_s10_sdram_probe,
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+ .remove = altr_s10_sdram_remove,
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+ .driver = {
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+ .name = "altr_s10_sdram_edac",
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+#ifdef CONFIG_PM
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+ .pm = &altr_sdram_pm_ops,
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+#endif
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+ .of_match_table = altr_sdram_ctrl_of_match,
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+ },
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+};
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+
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+module_platform_driver(altr_s10_sdram_edac_driver);
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+
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/************************* EDAC Parent Probe *************************/
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static const struct of_device_id altr_edac_device_of_match[];
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@@ -1106,7 +1415,7 @@ static void *ocram_alloc_mem(size_t size, void **other)
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static void ocram_free_mem(void *p, size_t size, void *other)
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{
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- gen_pool_free((struct gen_pool *)other, (u32)p, size);
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+ gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
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}
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static const struct edac_device_prv_data ocramecc_data = {
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@@ -1925,6 +2234,171 @@ static struct platform_driver altr_edac_a10_driver = {
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};
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module_platform_driver(altr_edac_a10_driver);
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+/************** Stratix 10 EDAC Device Controller Functions> ************/
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+
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+#define to_s10edac(p, m) container_of(p, struct altr_stratix10_edac, m)
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+
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+/*
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+ * The double bit error is handled through SError which is fatal. This is
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+ * called as a panic notifier to printout ECC error info as part of the panic.
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+ */
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+static int s10_edac_dberr_handler(struct notifier_block *this,
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+ unsigned long event, void *ptr)
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+{
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+ struct altr_stratix10_edac *edac = to_s10edac(this, panic_notifier);
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+ int err_addr, dberror;
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+
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+ s10_protected_reg_read(edac, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
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+ &dberror);
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+ /* Remember the UE Errors for a reboot */
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+ s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, dberror);
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+ if (dberror & S10_DDR0_IRQ_MASK) {
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+ s10_protected_reg_read(edac, S10_DERRADDR_OFST, &err_addr);
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+ /* Remember the UE Error address */
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+ s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST,
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+ err_addr);
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+ edac_printk(KERN_ERR, EDAC_MC,
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+ "EDAC: [Uncorrectable errors @ 0x%08X]\n\n",
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+ err_addr);
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+ }
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+
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+ return NOTIFY_DONE;
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+}
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+
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+static void altr_edac_s10_irq_handler(struct irq_desc *desc)
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+{
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+ struct altr_stratix10_edac *edac = irq_desc_get_handler_data(desc);
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+ struct irq_chip *chip = irq_desc_get_chip(desc);
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+ int irq = irq_desc_get_irq(desc);
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+ int bit, sm_offset, irq_status;
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+
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+ sm_offset = S10_SYSMGR_ECC_INTSTAT_SERR_OFST;
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+
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+ chained_irq_enter(chip, desc);
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+
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+ s10_protected_reg_read(NULL, sm_offset, &irq_status);
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+
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+ for_each_set_bit(bit, (unsigned long *)&irq_status, 32) {
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+ irq = irq_linear_revmap(edac->domain, bit);
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+ if (irq)
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+ generic_handle_irq(irq);
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+ }
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+
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+ chained_irq_exit(chip, desc);
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+}
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+
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+static void s10_eccmgr_irq_mask(struct irq_data *d)
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+{
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+ struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d);
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+
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+ s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_SET_OFST,
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+ BIT(d->hwirq));
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+}
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+
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+static void s10_eccmgr_irq_unmask(struct irq_data *d)
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+{
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+ struct altr_stratix10_edac *edac = irq_data_get_irq_chip_data(d);
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+
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+ s10_protected_reg_write(edac, S10_SYSMGR_ECC_INTMASK_CLR_OFST,
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+ BIT(d->hwirq));
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+}
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+
|
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+static int s10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
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+ irq_hw_number_t hwirq)
|
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|
+{
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|
+ struct altr_stratix10_edac *edac = d->host_data;
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+
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+ irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
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+ irq_set_chip_data(irq, edac);
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+ irq_set_noprobe(irq);
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+
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|
+ return 0;
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|
+}
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+
|
|
|
+static const struct irq_domain_ops s10_eccmgr_ic_ops = {
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|
|
+ .map = s10_eccmgr_irqdomain_map,
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|
|
+ .xlate = irq_domain_xlate_twocell,
|
|
|
+};
|
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|
+
|
|
|
+static int altr_edac_s10_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct altr_stratix10_edac *edac;
|
|
|
+ struct device_node *child;
|
|
|
+ int dberror, err_addr;
|
|
|
+
|
|
|
+ edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
|
|
|
+ if (!edac)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ edac->dev = &pdev->dev;
|
|
|
+ platform_set_drvdata(pdev, edac);
|
|
|
+ INIT_LIST_HEAD(&edac->s10_ecc_devices);
|
|
|
+
|
|
|
+ edac->irq_chip.name = pdev->dev.of_node->name;
|
|
|
+ edac->irq_chip.irq_mask = s10_eccmgr_irq_mask;
|
|
|
+ edac->irq_chip.irq_unmask = s10_eccmgr_irq_unmask;
|
|
|
+ edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
|
|
|
+ &s10_eccmgr_ic_ops, edac);
|
|
|
+ if (!edac->domain) {
|
|
|
+ dev_err(&pdev->dev, "Error adding IRQ domain\n");
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+
|
|
|
+ edac->sb_irq = platform_get_irq(pdev, 0);
|
|
|
+ if (edac->sb_irq < 0) {
|
|
|
+ dev_err(&pdev->dev, "No SBERR IRQ resource\n");
|
|
|
+ return edac->sb_irq;
|
|
|
+ }
|
|
|
+
|
|
|
+ irq_set_chained_handler_and_data(edac->sb_irq,
|
|
|
+ altr_edac_s10_irq_handler,
|
|
|
+ edac);
|
|
|
+
|
|
|
+ edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
|
|
|
+ atomic_notifier_chain_register(&panic_notifier_list,
|
|
|
+ &edac->panic_notifier);
|
|
|
+
|
|
|
+ /* Printout a message if uncorrectable error previously. */
|
|
|
+ s10_protected_reg_read(edac, S10_SYSMGR_UE_VAL_OFST, &dberror);
|
|
|
+ if (dberror) {
|
|
|
+ s10_protected_reg_read(edac, S10_SYSMGR_UE_ADDR_OFST,
|
|
|
+ &err_addr);
|
|
|
+ edac_printk(KERN_ERR, EDAC_DEVICE,
|
|
|
+ "Previous Boot UE detected[0x%X] @ 0x%X\n",
|
|
|
+ dberror, err_addr);
|
|
|
+ /* Reset the sticky registers */
|
|
|
+ s10_protected_reg_write(edac, S10_SYSMGR_UE_VAL_OFST, 0);
|
|
|
+ s10_protected_reg_write(edac, S10_SYSMGR_UE_ADDR_OFST, 0);
|
|
|
+ }
|
|
|
+
|
|
|
+ for_each_child_of_node(pdev->dev.of_node, child) {
|
|
|
+ if (!of_device_is_available(child))
|
|
|
+ continue;
|
|
|
+
|
|
|
+ if (of_device_is_compatible(child, "altr,sdram-edac-s10"))
|
|
|
+ of_platform_populate(pdev->dev.of_node,
|
|
|
+ altr_sdram_ctrl_of_match,
|
|
|
+ NULL, &pdev->dev);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static const struct of_device_id altr_edac_s10_of_match[] = {
|
|
|
+ { .compatible = "altr,socfpga-s10-ecc-manager" },
|
|
|
+ {},
|
|
|
+};
|
|
|
+MODULE_DEVICE_TABLE(of, altr_edac_s10_of_match);
|
|
|
+
|
|
|
+static struct platform_driver altr_edac_s10_driver = {
|
|
|
+ .probe = altr_edac_s10_probe,
|
|
|
+ .driver = {
|
|
|
+ .name = "socfpga_s10_ecc_manager",
|
|
|
+ .of_match_table = altr_edac_s10_of_match,
|
|
|
+ },
|
|
|
+};
|
|
|
+module_platform_driver(altr_edac_s10_driver);
|
|
|
+
|
|
|
MODULE_LICENSE("GPL v2");
|
|
|
MODULE_AUTHOR("Thor Thayer");
|
|
|
MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
|
Linus Torvalds