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@@ -0,0 +1,334 @@
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+/*
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+ * Low level PM code for TI EMIF
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+ *
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+ * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
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+ * Dave Gerlach
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation version 2.
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+ *
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+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
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+ * kind, whether express or implied; without even the implied warranty
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+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#include <generated/ti-emif-asm-offsets.h>
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+#include <linux/linkage.h>
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+#include <asm/assembler.h>
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+#include <asm/memory.h>
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+
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+#include "emif.h"
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+
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+#define EMIF_POWER_MGMT_WAIT_SELF_REFRESH_8192_CYCLES 0x00a0
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+#define EMIF_POWER_MGMT_SR_TIMER_MASK 0x00f0
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+#define EMIF_POWER_MGMT_SELF_REFRESH_MODE 0x0200
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+#define EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK 0x0700
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+
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+#define EMIF_SDCFG_TYPE_DDR2 0x2 << SDRAM_TYPE_SHIFT
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+#define EMIF_STATUS_READY 0x4
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+
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+#define AM43XX_EMIF_PHY_CTRL_REG_COUNT 0x120
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+
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+#define EMIF_AM437X_REGISTERS 0x1
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+
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+ .arm
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+ .align 3
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+
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+ENTRY(ti_emif_sram)
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+
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+/*
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+ * void ti_emif_save_context(void)
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+ *
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+ * Used during suspend to save the context of all required EMIF registers
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+ * to local memory if the EMIF is going to lose context during the sleep
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+ * transition. Operates on the VIRTUAL address of the EMIF.
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+ */
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+ENTRY(ti_emif_save_context)
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+ stmfd sp!, {r4 - r11, lr} @ save registers on stack
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+
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+ adr r4, ti_emif_pm_sram_data
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+ ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
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+ ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
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+
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+ /* Save EMIF configuration */
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+ ldr r1, [r0, #EMIF_SDRAM_CONFIG]
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+ str r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
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+ str r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
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+ str r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
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+ str r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
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+ str r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
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+ str r1, [r2, #EMIF_PMCR_VAL_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
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+ str r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
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+ str r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_DDR_PHY_CTRL_1]
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+ str r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_COS_CONFIG]
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+ str r1, [r2, #EMIF_COS_CONFIG_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
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+ str r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
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+ str r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
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+ str r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_OCP_CONFIG]
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+ str r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
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+
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+ ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
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+ cmp r5, #EMIF_SRAM_AM43_REG_LAYOUT
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+ bne emif_skip_save_extra_regs
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+
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+ ldr r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
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+ str r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
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+ str r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
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+ str r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
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+ str r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_DLL_CALIB_CTRL]
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+ str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
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+ str r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
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+
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+ /* Loop and save entire block of emif phy regs */
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+ mov r5, #0x0
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+ add r4, r2, #EMIF_EXT_PHY_CTRL_VALS_OFFSET
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+ add r3, r0, #EMIF_EXT_PHY_CTRL_1
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+ddr_phy_ctrl_save:
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+ ldr r1, [r3, r5]
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+ str r1, [r4, r5]
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+ add r5, r5, #0x4
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+ cmp r5, #AM43XX_EMIF_PHY_CTRL_REG_COUNT
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+ bne ddr_phy_ctrl_save
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+
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+emif_skip_save_extra_regs:
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+ ldmfd sp!, {r4 - r11, pc} @ restore regs and return
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+ENDPROC(ti_emif_save_context)
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+
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+/*
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+ * void ti_emif_restore_context(void)
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+ *
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+ * Used during resume to restore the context of all required EMIF registers
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+ * from local memory after the EMIF has lost context during a sleep transition.
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+ * Operates on the PHYSICAL address of the EMIF.
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+ */
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+ENTRY(ti_emif_restore_context)
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+ adr r4, ti_emif_pm_sram_data
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+ ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
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+ ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
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+
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+ /* Config EMIF Timings */
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+ ldr r1, [r2, #EMIF_DDR_PHY_CTLR_1_OFFSET]
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+ str r1, [r0, #EMIF_DDR_PHY_CTRL_1]
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+ str r1, [r0, #EMIF_DDR_PHY_CTRL_1_SHDW]
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+
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+ ldr r1, [r2, #EMIF_TIMING1_VAL_OFFSET]
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+ str r1, [r0, #EMIF_SDRAM_TIMING_1]
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+ str r1, [r0, #EMIF_SDRAM_TIMING_1_SHDW]
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+
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+ ldr r1, [r2, #EMIF_TIMING2_VAL_OFFSET]
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+ str r1, [r0, #EMIF_SDRAM_TIMING_2]
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+ str r1, [r0, #EMIF_SDRAM_TIMING_2_SHDW]
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+
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+ ldr r1, [r2, #EMIF_TIMING3_VAL_OFFSET]
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+ str r1, [r0, #EMIF_SDRAM_TIMING_3]
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+ str r1, [r0, #EMIF_SDRAM_TIMING_3_SHDW]
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+
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+ ldr r1, [r2, #EMIF_REF_CTRL_VAL_OFFSET]
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+ str r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
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+ str r1, [r0, #EMIF_SDRAM_REFRESH_CTRL_SHDW]
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+
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+ ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
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+ str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
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+
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+ ldr r1, [r2, #EMIF_PMCR_SHDW_VAL_OFFSET]
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+ str r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
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+
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+ ldr r1, [r2, #EMIF_COS_CONFIG_OFFSET]
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+ str r1, [r0, #EMIF_COS_CONFIG]
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+
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+ ldr r1, [r2, #EMIF_PRIORITY_TO_COS_MAPPING_OFFSET]
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+ str r1, [r0, #EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING]
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+
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+ ldr r1, [r2, #EMIF_CONNECT_ID_SERV_1_MAP_OFFSET]
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+ str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING]
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+
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+ ldr r1, [r2, #EMIF_CONNECT_ID_SERV_2_MAP_OFFSET]
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+ str r1, [r0, #EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING]
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+
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+ ldr r1, [r2, #EMIF_OCP_CONFIG_VAL_OFFSET]
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+ str r1, [r0, #EMIF_OCP_CONFIG]
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+
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+ ldr r5, [r4, #EMIF_PM_CONFIG_OFFSET]
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+ cmp r5, #EMIF_SRAM_AM43_REG_LAYOUT
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+ bne emif_skip_restore_extra_regs
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+
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+ ldr r1, [r2, #EMIF_RD_WR_LEVEL_RAMP_CTRL_OFFSET]
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+ str r1, [r0, #EMIF_READ_WRITE_LEVELING_RAMP_CONTROL]
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+
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+ ldr r1, [r2, #EMIF_RD_WR_EXEC_THRESH_OFFSET]
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+ str r1, [r0, #EMIF_READ_WRITE_EXECUTION_THRESHOLD]
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+
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+ ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_OFFSET]
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+ str r1, [r0, #EMIF_LPDDR2_NVM_TIMING]
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+
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+ ldr r1, [r2, #EMIF_LPDDR2_NVM_TIM_SHDW_OFFSET]
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+ str r1, [r0, #EMIF_LPDDR2_NVM_TIMING_SHDW]
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+
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+ ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_OFFSET]
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+ str r1, [r0, #EMIF_DLL_CALIB_CTRL]
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+
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+ ldr r1, [r2, #EMIF_DLL_CALIB_CTRL_VAL_SHDW_OFFSET]
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+ str r1, [r0, #EMIF_DLL_CALIB_CTRL_SHDW]
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+
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+ ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
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+ str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
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+
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+ /* Loop and restore entire block of emif phy regs */
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+ mov r5, #0x0
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+ /* Load ti_emif_regs_amx3 + EMIF_EXT_PHY_CTRL_VALS_OFFSET for address
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+ * to phy register save space
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+ */
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+ add r3, r2, #EMIF_EXT_PHY_CTRL_VALS_OFFSET
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+ add r4, r0, #EMIF_EXT_PHY_CTRL_1
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+ddr_phy_ctrl_restore:
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+ ldr r1, [r3, r5]
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+ str r1, [r4, r5]
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+ add r5, r5, #0x4
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+ cmp r5, #AM43XX_EMIF_PHY_CTRL_REG_COUNT
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+ bne ddr_phy_ctrl_restore
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+
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+emif_skip_restore_extra_regs:
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+ /*
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+ * Output impedence calib needed only for DDR3
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+ * but since the initial state of this will be
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+ * disabled for DDR2 no harm in restoring the
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+ * old configuration
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+ */
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+ ldr r1, [r2, #EMIF_ZQCFG_VAL_OFFSET]
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+ str r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
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+
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+ /* Write to sdcfg last for DDR2 only */
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+ ldr r1, [r2, #EMIF_SDCFG_VAL_OFFSET]
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+ and r2, r1, #SDRAM_TYPE_MASK
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+ cmp r2, #EMIF_SDCFG_TYPE_DDR2
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+ streq r1, [r0, #EMIF_SDRAM_CONFIG]
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+
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+ mov pc, lr
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+ENDPROC(ti_emif_restore_context)
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+
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+/*
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+ * void ti_emif_enter_sr(void)
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+ *
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+ * Programs the EMIF to tell the SDRAM to enter into self-refresh
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+ * mode during a sleep transition. Operates on the VIRTUAL address
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+ * of the EMIF.
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+ */
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+ENTRY(ti_emif_enter_sr)
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+ stmfd sp!, {r4 - r11, lr} @ save registers on stack
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+
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+ adr r4, ti_emif_pm_sram_data
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+ ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
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+ ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
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+
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+ ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
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+ bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
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+ orr r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
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+ str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
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+
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+ ldmfd sp!, {r4 - r11, pc} @ restore regs and return
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+ENDPROC(ti_emif_enter_sr)
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+
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+/*
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+ * void ti_emif_exit_sr(void)
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+ *
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+ * Programs the EMIF to tell the SDRAM to exit self-refresh mode
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+ * after a sleep transition. Operates on the PHYSICAL address of
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+ * the EMIF.
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+ */
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+ENTRY(ti_emif_exit_sr)
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+ adr r4, ti_emif_pm_sram_data
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+ ldr r0, [r4, #EMIF_PM_BASE_ADDR_PHYS_OFFSET]
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+ ldr r2, [r4, #EMIF_PM_REGS_PHYS_OFFSET]
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+
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+ /*
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+ * Toggle EMIF to exit refresh mode:
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+ * if EMIF lost context, PWR_MGT_CTRL is currently 0, writing disable
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+ * (0x0), wont do diddly squat! so do a toggle from SR(0x2) to disable
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+ * (0x0) here.
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+ * *If* EMIF did not lose context, nothing broken as we write the same
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+ * value(0x2) to reg before we write a disable (0x0).
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+ */
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+ ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
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+ bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
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+ orr r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE
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+ str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
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+ bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
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+ str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
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+
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+ /* Wait for EMIF to become ready */
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+1: ldr r1, [r0, #EMIF_STATUS]
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+ tst r1, #EMIF_STATUS_READY
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+ beq 1b
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+
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+ mov pc, lr
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+ENDPROC(ti_emif_exit_sr)
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+
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+/*
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+ * void ti_emif_abort_sr(void)
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+ *
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+ * Disables self-refresh after a failed transition to a low-power
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+ * state so the kernel can jump back to DDR and follow abort path.
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+ * Operates on the VIRTUAL address of the EMIF.
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+ */
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+ENTRY(ti_emif_abort_sr)
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+ stmfd sp!, {r4 - r11, lr} @ save registers on stack
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+
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+ adr r4, ti_emif_pm_sram_data
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+ ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
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+ ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
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+
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+ ldr r1, [r2, #EMIF_PMCR_VAL_OFFSET]
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+ bic r1, r1, #EMIF_POWER_MGMT_SELF_REFRESH_MODE_MASK
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+ str r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
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+
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+ /* Wait for EMIF to become ready */
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+1: ldr r1, [r0, #EMIF_STATUS]
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+ tst r1, #EMIF_STATUS_READY
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+ beq 1b
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+
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+ ldmfd sp!, {r4 - r11, pc} @ restore regs and return
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+ENDPROC(ti_emif_abort_sr)
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+
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+ .align 3
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+ENTRY(ti_emif_pm_sram_data)
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+ .space EMIF_PM_DATA_SIZE
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+ENTRY(ti_emif_sram_sz)
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+ .word . - ti_emif_save_context
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Dave Gerlach