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+STMicroelectronics STM32 ADC device driver
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+
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+STM32 ADC is a successive approximation analog-to-digital converter.
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+It has several multiplexed input channels. Conversions can be performed
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+in single, continuous, scan or discontinuous mode. Result of the ADC is
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+stored in a left-aligned or right-aligned 32-bit data register.
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+Conversions can be launched in software or using hardware triggers.
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+
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+The analog watchdog feature allows the application to detect if the input
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+voltage goes beyond the user-defined, higher or lower thresholds.
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+
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+Each STM32 ADC block can have up to 3 ADC instances.
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+
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+Each instance supports two contexts to manage conversions, each one has its
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+own configurable sequence and trigger:
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+- regular conversion can be done in sequence, running in background
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+- injected conversions have higher priority, and so have the ability to
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+ interrupt regular conversion sequence (either triggered in SW or HW).
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+ Regular sequence is resumed, in case it has been interrupted.
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+
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+Contents of a stm32 adc root node:
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+-----------------------------------
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+Required properties:
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+- compatible: Should be "st,stm32f4-adc-core".
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+- reg: Offset and length of the ADC block register set.
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+- interrupts: Must contain the interrupt for ADC block.
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+- clocks: Clock for the analog circuitry (common to all ADCs).
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+- clock-names: Must be "adc".
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+- interrupt-controller: Identifies the controller node as interrupt-parent
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+- vref-supply: Phandle to the vref input analog reference voltage.
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+- #interrupt-cells = <1>;
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+- #address-cells = <1>;
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+- #size-cells = <0>;
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+
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+Optional properties:
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+- A pinctrl state named "default" for each ADC channel may be defined to set
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+ inX ADC pins in mode of operation for analog input on external pin.
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+
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+Contents of a stm32 adc child node:
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+-----------------------------------
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+An ADC block node should contain at least one subnode, representing an
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+ADC instance available on the machine.
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+
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+Required properties:
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+- compatible: Should be "st,stm32f4-adc".
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+- reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200).
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+- clocks: Input clock private to this ADC instance.
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+- interrupt-parent: Phandle to the parent interrupt controller.
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+- interrupts: IRQ Line for the ADC (e.g. may be 0 for adc@0, 1 for adc@100 or
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+ 2 for adc@200).
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+- st,adc-channels: List of single-ended channels muxed for this ADC.
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+ It can have up to 16 channels, numbered from 0 to 15 (resp. for in0..in15).
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+- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
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+ Documentation/devicetree/bindings/iio/iio-bindings.txt
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+
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+Example:
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+ adc: adc@40012000 {
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+ compatible = "st,stm32f4-adc-core";
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+ reg = <0x40012000 0x400>;
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+ interrupts = <18>;
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+ clocks = <&rcc 0 168>;
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+ clock-names = "adc";
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+ vref-supply = <®_vref>;
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+ interrupt-controller;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&adc3_in8_pin>;
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+
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+ #interrupt-cells = <1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ adc@0 {
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+ compatible = "st,stm32f4-adc";
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+ #io-channel-cells = <1>;
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+ reg = <0x0>;
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+ clocks = <&rcc 0 168>;
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+ interrupt-parent = <&adc>;
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+ interrupts = <0>;
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+ st,adc-channels = <8>;
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+ };
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+ ...
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+ other adc child nodes follow...
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+ };
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