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@@ -682,7 +682,10 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
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adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
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if (!adev->mc.vram_width) {
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/* hbm memory channel size */
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- chansize = 128;
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+ if (adev->flags & AMD_IS_APU)
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+ chansize = 64;
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+ else
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+ chansize = 128;
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tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
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tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
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