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@@ -216,23 +216,23 @@ static bool wm8900_volatile_register(struct device *dev, unsigned int reg)
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}
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}
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-static void wm8900_reset(struct snd_soc_codec *codec)
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+static void wm8900_reset(struct snd_soc_component *component)
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{
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- snd_soc_write(codec, WM8900_REG_RESET, 0);
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+ snd_soc_component_write(component, WM8900_REG_RESET, 0);
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}
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static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
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struct snd_kcontrol *kcontrol, int event)
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{
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- struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
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- u16 hpctl1 = snd_soc_read(codec, WM8900_REG_HPCTL1);
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+ struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
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+ u16 hpctl1 = snd_soc_component_read32(component, WM8900_REG_HPCTL1);
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switch (event) {
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case SND_SOC_DAPM_PRE_PMU:
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/* Clamp headphone outputs */
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hpctl1 = WM8900_REG_HPCTL1_HP_CLAMP_IP |
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WM8900_REG_HPCTL1_HP_CLAMP_OP;
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- snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
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+ snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
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break;
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case SND_SOC_DAPM_POST_PMU:
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@@ -241,41 +241,41 @@ static int wm8900_hp_event(struct snd_soc_dapm_widget *w,
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hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT |
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WM8900_REG_HPCTL1_HP_SHORT2 |
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WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
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- snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
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+ snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
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msleep(400);
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/* Enable the output stage */
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hpctl1 &= ~WM8900_REG_HPCTL1_HP_CLAMP_OP;
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hpctl1 |= WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
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- snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
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+ snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
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/* Remove the shorts */
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hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT2;
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- snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
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+ snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
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hpctl1 &= ~WM8900_REG_HPCTL1_HP_SHORT;
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- snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
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+ snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
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break;
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case SND_SOC_DAPM_PRE_PMD:
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/* Short the output */
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hpctl1 |= WM8900_REG_HPCTL1_HP_SHORT;
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- snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
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+ snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
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/* Disable the output stage */
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hpctl1 &= ~WM8900_REG_HPCTL1_HP_OPSTAGE_ENA;
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- snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
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+ snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
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/* Clamp the outputs and power down input */
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hpctl1 |= WM8900_REG_HPCTL1_HP_CLAMP_IP |
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WM8900_REG_HPCTL1_HP_CLAMP_OP;
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hpctl1 &= ~WM8900_REG_HPCTL1_HP_IPSTAGE_ENA;
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- snd_soc_write(codec, WM8900_REG_HPCTL1, hpctl1);
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+ snd_soc_component_write(component, WM8900_REG_HPCTL1, hpctl1);
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break;
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case SND_SOC_DAPM_POST_PMD:
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/* Disable everything */
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- snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
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+ snd_soc_component_write(component, WM8900_REG_HPCTL1, 0);
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break;
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default:
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@@ -635,10 +635,10 @@ static int wm8900_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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- struct snd_soc_codec *codec = dai->codec;
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+ struct snd_soc_component *component = dai->component;
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u16 reg;
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- reg = snd_soc_read(codec, WM8900_REG_AUDIO1) & ~0x60;
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+ reg = snd_soc_component_read32(component, WM8900_REG_AUDIO1) & ~0x60;
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switch (params_width(params)) {
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case 16:
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@@ -656,17 +656,17 @@ static int wm8900_hw_params(struct snd_pcm_substream *substream,
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return -EINVAL;
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}
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- snd_soc_write(codec, WM8900_REG_AUDIO1, reg);
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+ snd_soc_component_write(component, WM8900_REG_AUDIO1, reg);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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- reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
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+ reg = snd_soc_component_read32(component, WM8900_REG_DACCTRL);
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if (params_rate(params) <= 24000)
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reg |= WM8900_REG_DACCTRL_DAC_SB_FILT;
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else
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reg &= ~WM8900_REG_DACCTRL_DAC_SB_FILT;
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- snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
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+ snd_soc_component_write(component, WM8900_REG_DACCTRL, reg);
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}
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return 0;
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@@ -751,24 +751,24 @@ static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
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return 0;
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}
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-static int wm8900_set_fll(struct snd_soc_codec *codec,
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+static int wm8900_set_fll(struct snd_soc_component *component,
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int fll_id, unsigned int freq_in, unsigned int freq_out)
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{
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- struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
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+ struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
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struct _fll_div fll_div;
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if (wm8900->fll_in == freq_in && wm8900->fll_out == freq_out)
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return 0;
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/* The digital side should be disabled during any change. */
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- snd_soc_update_bits(codec, WM8900_REG_POWER1,
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+ snd_soc_component_update_bits(component, WM8900_REG_POWER1,
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WM8900_REG_POWER1_FLL_ENA, 0);
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/* Disable the FLL? */
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if (!freq_in || !freq_out) {
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- snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
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+ snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
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WM8900_REG_CLOCKING1_MCLK_SRC, 0);
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- snd_soc_update_bits(codec, WM8900_REG_FLLCTL1,
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+ snd_soc_component_update_bits(component, WM8900_REG_FLLCTL1,
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WM8900_REG_FLLCTL1_OSC_ENA, 0);
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wm8900->fll_in = freq_in;
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wm8900->fll_out = freq_out;
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@@ -784,32 +784,32 @@ static int wm8900_set_fll(struct snd_soc_codec *codec,
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/* The osclilator *MUST* be enabled before we enable the
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* digital circuit. */
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- snd_soc_write(codec, WM8900_REG_FLLCTL1,
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+ snd_soc_component_write(component, WM8900_REG_FLLCTL1,
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fll_div.fll_ratio | WM8900_REG_FLLCTL1_OSC_ENA);
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- snd_soc_write(codec, WM8900_REG_FLLCTL4, fll_div.n >> 5);
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- snd_soc_write(codec, WM8900_REG_FLLCTL5,
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+ snd_soc_component_write(component, WM8900_REG_FLLCTL4, fll_div.n >> 5);
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+ snd_soc_component_write(component, WM8900_REG_FLLCTL5,
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(fll_div.fllclk_div << 6) | (fll_div.n & 0x1f));
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if (fll_div.k) {
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- snd_soc_write(codec, WM8900_REG_FLLCTL2,
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+ snd_soc_component_write(component, WM8900_REG_FLLCTL2,
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(fll_div.k >> 8) | 0x100);
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- snd_soc_write(codec, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
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+ snd_soc_component_write(component, WM8900_REG_FLLCTL3, fll_div.k & 0xff);
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} else
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- snd_soc_write(codec, WM8900_REG_FLLCTL2, 0);
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+ snd_soc_component_write(component, WM8900_REG_FLLCTL2, 0);
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if (fll_div.fll_slow_lock_ref)
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- snd_soc_write(codec, WM8900_REG_FLLCTL6,
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+ snd_soc_component_write(component, WM8900_REG_FLLCTL6,
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WM8900_REG_FLLCTL6_FLL_SLOW_LOCK_REF);
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else
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- snd_soc_write(codec, WM8900_REG_FLLCTL6, 0);
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+ snd_soc_component_write(component, WM8900_REG_FLLCTL6, 0);
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- snd_soc_update_bits(codec, WM8900_REG_POWER1,
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+ snd_soc_component_update_bits(component, WM8900_REG_POWER1,
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WM8900_REG_POWER1_FLL_ENA,
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WM8900_REG_POWER1_FLL_ENA);
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reenable:
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- snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
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+ snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
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WM8900_REG_CLOCKING1_MCLK_SRC,
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WM8900_REG_CLOCKING1_MCLK_SRC);
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return 0;
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@@ -818,41 +818,41 @@ reenable:
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static int wm8900_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
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int source, unsigned int freq_in, unsigned int freq_out)
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{
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- return wm8900_set_fll(codec_dai->codec, pll_id, freq_in, freq_out);
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+ return wm8900_set_fll(codec_dai->component, pll_id, freq_in, freq_out);
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}
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static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
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int div_id, int div)
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{
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- struct snd_soc_codec *codec = codec_dai->codec;
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+ struct snd_soc_component *component = codec_dai->component;
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switch (div_id) {
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case WM8900_BCLK_DIV:
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- snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
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+ snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
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WM8900_REG_CLOCKING1_BCLK_MASK, div);
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break;
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case WM8900_OPCLK_DIV:
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- snd_soc_update_bits(codec, WM8900_REG_CLOCKING1,
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+ snd_soc_component_update_bits(component, WM8900_REG_CLOCKING1,
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WM8900_REG_CLOCKING1_OPCLK_MASK, div);
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break;
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case WM8900_DAC_LRCLK:
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- snd_soc_update_bits(codec, WM8900_REG_AUDIO4,
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+ snd_soc_component_update_bits(component, WM8900_REG_AUDIO4,
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WM8900_LRC_MASK, div);
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break;
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case WM8900_ADC_LRCLK:
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- snd_soc_update_bits(codec, WM8900_REG_AUDIO3,
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+ snd_soc_component_update_bits(component, WM8900_REG_AUDIO3,
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WM8900_LRC_MASK, div);
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break;
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case WM8900_DAC_CLKDIV:
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- snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
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+ snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2,
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WM8900_REG_CLOCKING2_DAC_CLKDIV, div);
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break;
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case WM8900_ADC_CLKDIV:
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- snd_soc_update_bits(codec, WM8900_REG_CLOCKING2,
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+ snd_soc_component_update_bits(component, WM8900_REG_CLOCKING2,
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WM8900_REG_CLOCKING2_ADC_CLKDIV, div);
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break;
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case WM8900_LRCLK_MODE:
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- snd_soc_update_bits(codec, WM8900_REG_DACCTRL,
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+ snd_soc_component_update_bits(component, WM8900_REG_DACCTRL,
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WM8900_REG_DACCTRL_AIF_LRCLKRATE, div);
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break;
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default:
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@@ -866,13 +866,13 @@ static int wm8900_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
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static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
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unsigned int fmt)
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{
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- struct snd_soc_codec *codec = codec_dai->codec;
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+ struct snd_soc_component *component = codec_dai->component;
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unsigned int clocking1, aif1, aif3, aif4;
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- clocking1 = snd_soc_read(codec, WM8900_REG_CLOCKING1);
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- aif1 = snd_soc_read(codec, WM8900_REG_AUDIO1);
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- aif3 = snd_soc_read(codec, WM8900_REG_AUDIO3);
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- aif4 = snd_soc_read(codec, WM8900_REG_AUDIO4);
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+ clocking1 = snd_soc_component_read32(component, WM8900_REG_CLOCKING1);
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+ aif1 = snd_soc_component_read32(component, WM8900_REG_AUDIO1);
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+ aif3 = snd_soc_component_read32(component, WM8900_REG_AUDIO3);
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+ aif4 = snd_soc_component_read32(component, WM8900_REG_AUDIO4);
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/* set master/slave audio interface */
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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@@ -968,27 +968,27 @@ static int wm8900_set_dai_fmt(struct snd_soc_dai *codec_dai,
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return -EINVAL;
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}
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- snd_soc_write(codec, WM8900_REG_CLOCKING1, clocking1);
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- snd_soc_write(codec, WM8900_REG_AUDIO1, aif1);
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- snd_soc_write(codec, WM8900_REG_AUDIO3, aif3);
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- snd_soc_write(codec, WM8900_REG_AUDIO4, aif4);
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+ snd_soc_component_write(component, WM8900_REG_CLOCKING1, clocking1);
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+ snd_soc_component_write(component, WM8900_REG_AUDIO1, aif1);
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+ snd_soc_component_write(component, WM8900_REG_AUDIO3, aif3);
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+ snd_soc_component_write(component, WM8900_REG_AUDIO4, aif4);
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return 0;
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}
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static int wm8900_digital_mute(struct snd_soc_dai *codec_dai, int mute)
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{
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- struct snd_soc_codec *codec = codec_dai->codec;
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+ struct snd_soc_component *component = codec_dai->component;
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u16 reg;
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- reg = snd_soc_read(codec, WM8900_REG_DACCTRL);
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+ reg = snd_soc_component_read32(component, WM8900_REG_DACCTRL);
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if (mute)
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reg |= WM8900_REG_DACCTRL_MUTE;
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else
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reg &= ~WM8900_REG_DACCTRL_MUTE;
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- snd_soc_write(codec, WM8900_REG_DACCTRL, reg);
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+ snd_soc_component_write(component, WM8900_REG_DACCTRL, reg);
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return 0;
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}
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@@ -1028,7 +1028,7 @@ static struct snd_soc_dai_driver wm8900_dai = {
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.ops = &wm8900_dai_ops,
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};
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-static int wm8900_set_bias_level(struct snd_soc_codec *codec,
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+static int wm8900_set_bias_level(struct snd_soc_component *component,
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enum snd_soc_bias_level level)
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{
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u16 reg;
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@@ -1036,10 +1036,10 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec,
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switch (level) {
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case SND_SOC_BIAS_ON:
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/* Enable thermal shutdown */
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- snd_soc_update_bits(codec, WM8900_REG_GPIO,
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+ snd_soc_component_update_bits(component, WM8900_REG_GPIO,
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WM8900_REG_GPIO_TEMP_ENA,
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WM8900_REG_GPIO_TEMP_ENA);
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- snd_soc_update_bits(codec, WM8900_REG_ADDCTL,
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+ snd_soc_component_update_bits(component, WM8900_REG_ADDCTL,
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WM8900_REG_ADDCTL_TEMP_SD,
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WM8900_REG_ADDCTL_TEMP_SD);
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break;
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@@ -1049,113 +1049,113 @@ static int wm8900_set_bias_level(struct snd_soc_codec *codec,
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case SND_SOC_BIAS_STANDBY:
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/* Charge capacitors if initial power up */
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- if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
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+ if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
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/* STARTUP_BIAS_ENA on */
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- snd_soc_write(codec, WM8900_REG_POWER1,
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+ snd_soc_component_write(component, WM8900_REG_POWER1,
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WM8900_REG_POWER1_STARTUP_BIAS_ENA);
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/* Startup bias mode */
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- snd_soc_write(codec, WM8900_REG_ADDCTL,
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+ snd_soc_component_write(component, WM8900_REG_ADDCTL,
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WM8900_REG_ADDCTL_BIAS_SRC |
|
|
|
WM8900_REG_ADDCTL_VMID_SOFTST);
|
|
|
|
|
|
/* VMID 2x50k */
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER1,
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER1,
|
|
|
WM8900_REG_POWER1_STARTUP_BIAS_ENA | 0x1);
|
|
|
|
|
|
/* Allow capacitors to charge */
|
|
|
schedule_timeout_interruptible(msecs_to_jiffies(400));
|
|
|
|
|
|
/* Enable bias */
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER1,
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER1,
|
|
|
WM8900_REG_POWER1_STARTUP_BIAS_ENA |
|
|
|
WM8900_REG_POWER1_BIAS_ENA | 0x1);
|
|
|
|
|
|
- snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
|
|
|
+ snd_soc_component_write(component, WM8900_REG_ADDCTL, 0);
|
|
|
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER1,
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER1,
|
|
|
WM8900_REG_POWER1_BIAS_ENA | 0x1);
|
|
|
}
|
|
|
|
|
|
- reg = snd_soc_read(codec, WM8900_REG_POWER1);
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER1,
|
|
|
+ reg = snd_soc_component_read32(component, WM8900_REG_POWER1);
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER1,
|
|
|
(reg & WM8900_REG_POWER1_FLL_ENA) |
|
|
|
WM8900_REG_POWER1_BIAS_ENA | 0x1);
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER2,
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER2,
|
|
|
WM8900_REG_POWER2_SYSCLK_ENA);
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER3, 0);
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER3, 0);
|
|
|
break;
|
|
|
|
|
|
case SND_SOC_BIAS_OFF:
|
|
|
/* Startup bias enable */
|
|
|
- reg = snd_soc_read(codec, WM8900_REG_POWER1);
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER1,
|
|
|
+ reg = snd_soc_component_read32(component, WM8900_REG_POWER1);
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER1,
|
|
|
reg & WM8900_REG_POWER1_STARTUP_BIAS_ENA);
|
|
|
- snd_soc_write(codec, WM8900_REG_ADDCTL,
|
|
|
+ snd_soc_component_write(component, WM8900_REG_ADDCTL,
|
|
|
WM8900_REG_ADDCTL_BIAS_SRC |
|
|
|
WM8900_REG_ADDCTL_VMID_SOFTST);
|
|
|
|
|
|
/* Discharge caps */
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER1,
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER1,
|
|
|
WM8900_REG_POWER1_STARTUP_BIAS_ENA);
|
|
|
schedule_timeout_interruptible(msecs_to_jiffies(500));
|
|
|
|
|
|
/* Remove clamp */
|
|
|
- snd_soc_write(codec, WM8900_REG_HPCTL1, 0);
|
|
|
+ snd_soc_component_write(component, WM8900_REG_HPCTL1, 0);
|
|
|
|
|
|
/* Power down */
|
|
|
- snd_soc_write(codec, WM8900_REG_ADDCTL, 0);
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER1, 0);
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER2, 0);
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER3, 0);
|
|
|
+ snd_soc_component_write(component, WM8900_REG_ADDCTL, 0);
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER1, 0);
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER2, 0);
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER3, 0);
|
|
|
|
|
|
/* Need to let things settle before stopping the clock
|
|
|
* to ensure that restart works, see "Stopping the
|
|
|
* master clock" in the datasheet. */
|
|
|
schedule_timeout_interruptible(msecs_to_jiffies(1));
|
|
|
- snd_soc_write(codec, WM8900_REG_POWER2,
|
|
|
+ snd_soc_component_write(component, WM8900_REG_POWER2,
|
|
|
WM8900_REG_POWER2_SYSCLK_ENA);
|
|
|
break;
|
|
|
}
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-static int wm8900_suspend(struct snd_soc_codec *codec)
|
|
|
+static int wm8900_suspend(struct snd_soc_component *component)
|
|
|
{
|
|
|
- struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
|
|
|
+ struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
|
|
|
int fll_out = wm8900->fll_out;
|
|
|
int fll_in = wm8900->fll_in;
|
|
|
int ret;
|
|
|
|
|
|
/* Stop the FLL in an orderly fashion */
|
|
|
- ret = wm8900_set_fll(codec, 0, 0, 0);
|
|
|
+ ret = wm8900_set_fll(component, 0, 0, 0);
|
|
|
if (ret != 0) {
|
|
|
- dev_err(codec->dev, "Failed to stop FLL\n");
|
|
|
+ dev_err(component->dev, "Failed to stop FLL\n");
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
wm8900->fll_out = fll_out;
|
|
|
wm8900->fll_in = fll_in;
|
|
|
|
|
|
- snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
|
|
|
+ snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-static int wm8900_resume(struct snd_soc_codec *codec)
|
|
|
+static int wm8900_resume(struct snd_soc_component *component)
|
|
|
{
|
|
|
- struct wm8900_priv *wm8900 = snd_soc_codec_get_drvdata(codec);
|
|
|
+ struct wm8900_priv *wm8900 = snd_soc_component_get_drvdata(component);
|
|
|
int ret;
|
|
|
|
|
|
- wm8900_reset(codec);
|
|
|
+ wm8900_reset(component);
|
|
|
|
|
|
ret = regcache_sync(wm8900->regmap);
|
|
|
if (ret != 0) {
|
|
|
- dev_err(codec->dev, "Failed to restore cache: %d\n", ret);
|
|
|
+ dev_err(component->dev, "Failed to restore cache: %d\n", ret);
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
- snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
|
|
+ snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
|
|
|
|
|
|
/* Restart the FLL? */
|
|
|
if (wm8900->fll_out) {
|
|
@@ -1165,9 +1165,9 @@ static int wm8900_resume(struct snd_soc_codec *codec)
|
|
|
wm8900->fll_in = 0;
|
|
|
wm8900->fll_out = 0;
|
|
|
|
|
|
- ret = wm8900_set_fll(codec, 0, fll_in, fll_out);
|
|
|
+ ret = wm8900_set_fll(component, 0, fll_in, fll_out);
|
|
|
if (ret != 0) {
|
|
|
- dev_err(codec->dev, "Failed to restart FLL\n");
|
|
|
+ dev_err(component->dev, "Failed to restart FLL\n");
|
|
|
return ret;
|
|
|
}
|
|
|
}
|
|
@@ -1175,53 +1175,54 @@ static int wm8900_resume(struct snd_soc_codec *codec)
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-static int wm8900_probe(struct snd_soc_codec *codec)
|
|
|
+static int wm8900_probe(struct snd_soc_component *component)
|
|
|
{
|
|
|
int reg;
|
|
|
|
|
|
- reg = snd_soc_read(codec, WM8900_REG_ID);
|
|
|
+ reg = snd_soc_component_read32(component, WM8900_REG_ID);
|
|
|
if (reg != 0x8900) {
|
|
|
- dev_err(codec->dev, "Device is not a WM8900 - ID %x\n", reg);
|
|
|
+ dev_err(component->dev, "Device is not a WM8900 - ID %x\n", reg);
|
|
|
return -ENODEV;
|
|
|
}
|
|
|
|
|
|
- wm8900_reset(codec);
|
|
|
+ wm8900_reset(component);
|
|
|
|
|
|
/* Turn the chip on */
|
|
|
- snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_STANDBY);
|
|
|
+ snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
|
|
|
|
|
|
/* Latch the volume update bits */
|
|
|
- snd_soc_update_bits(codec, WM8900_REG_LINVOL, 0x100, 0x100);
|
|
|
- snd_soc_update_bits(codec, WM8900_REG_RINVOL, 0x100, 0x100);
|
|
|
- snd_soc_update_bits(codec, WM8900_REG_LOUT1CTL, 0x100, 0x100);
|
|
|
- snd_soc_update_bits(codec, WM8900_REG_ROUT1CTL, 0x100, 0x100);
|
|
|
- snd_soc_update_bits(codec, WM8900_REG_LOUT2CTL, 0x100, 0x100);
|
|
|
- snd_soc_update_bits(codec, WM8900_REG_ROUT2CTL, 0x100, 0x100);
|
|
|
- snd_soc_update_bits(codec, WM8900_REG_LDAC_DV, 0x100, 0x100);
|
|
|
- snd_soc_update_bits(codec, WM8900_REG_RDAC_DV, 0x100, 0x100);
|
|
|
- snd_soc_update_bits(codec, WM8900_REG_LADC_DV, 0x100, 0x100);
|
|
|
- snd_soc_update_bits(codec, WM8900_REG_RADC_DV, 0x100, 0x100);
|
|
|
+ snd_soc_component_update_bits(component, WM8900_REG_LINVOL, 0x100, 0x100);
|
|
|
+ snd_soc_component_update_bits(component, WM8900_REG_RINVOL, 0x100, 0x100);
|
|
|
+ snd_soc_component_update_bits(component, WM8900_REG_LOUT1CTL, 0x100, 0x100);
|
|
|
+ snd_soc_component_update_bits(component, WM8900_REG_ROUT1CTL, 0x100, 0x100);
|
|
|
+ snd_soc_component_update_bits(component, WM8900_REG_LOUT2CTL, 0x100, 0x100);
|
|
|
+ snd_soc_component_update_bits(component, WM8900_REG_ROUT2CTL, 0x100, 0x100);
|
|
|
+ snd_soc_component_update_bits(component, WM8900_REG_LDAC_DV, 0x100, 0x100);
|
|
|
+ snd_soc_component_update_bits(component, WM8900_REG_RDAC_DV, 0x100, 0x100);
|
|
|
+ snd_soc_component_update_bits(component, WM8900_REG_LADC_DV, 0x100, 0x100);
|
|
|
+ snd_soc_component_update_bits(component, WM8900_REG_RADC_DV, 0x100, 0x100);
|
|
|
|
|
|
/* Set the DAC and mixer output bias */
|
|
|
- snd_soc_write(codec, WM8900_REG_OUTBIASCTL, 0x81);
|
|
|
+ snd_soc_component_write(component, WM8900_REG_OUTBIASCTL, 0x81);
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-static const struct snd_soc_codec_driver soc_codec_dev_wm8900 = {
|
|
|
- .probe = wm8900_probe,
|
|
|
- .suspend = wm8900_suspend,
|
|
|
- .resume = wm8900_resume,
|
|
|
- .set_bias_level = wm8900_set_bias_level,
|
|
|
-
|
|
|
- .component_driver = {
|
|
|
- .controls = wm8900_snd_controls,
|
|
|
- .num_controls = ARRAY_SIZE(wm8900_snd_controls),
|
|
|
- .dapm_widgets = wm8900_dapm_widgets,
|
|
|
- .num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets),
|
|
|
- .dapm_routes = wm8900_dapm_routes,
|
|
|
- .num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes),
|
|
|
- },
|
|
|
+static const struct snd_soc_component_driver soc_component_dev_wm8900 = {
|
|
|
+ .probe = wm8900_probe,
|
|
|
+ .suspend = wm8900_suspend,
|
|
|
+ .resume = wm8900_resume,
|
|
|
+ .set_bias_level = wm8900_set_bias_level,
|
|
|
+ .controls = wm8900_snd_controls,
|
|
|
+ .num_controls = ARRAY_SIZE(wm8900_snd_controls),
|
|
|
+ .dapm_widgets = wm8900_dapm_widgets,
|
|
|
+ .num_dapm_widgets = ARRAY_SIZE(wm8900_dapm_widgets),
|
|
|
+ .dapm_routes = wm8900_dapm_routes,
|
|
|
+ .num_dapm_routes = ARRAY_SIZE(wm8900_dapm_routes),
|
|
|
+ .idle_bias_on = 1,
|
|
|
+ .use_pmdown_time = 1,
|
|
|
+ .endianness = 1,
|
|
|
+ .non_legacy_dai_naming = 1,
|
|
|
};
|
|
|
|
|
|
static const struct regmap_config wm8900_regmap = {
|
|
@@ -1253,15 +1254,14 @@ static int wm8900_spi_probe(struct spi_device *spi)
|
|
|
|
|
|
spi_set_drvdata(spi, wm8900);
|
|
|
|
|
|
- ret = snd_soc_register_codec(&spi->dev,
|
|
|
- &soc_codec_dev_wm8900, &wm8900_dai, 1);
|
|
|
+ ret = devm_snd_soc_register_component(&spi->dev,
|
|
|
+ &soc_component_dev_wm8900, &wm8900_dai, 1);
|
|
|
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
static int wm8900_spi_remove(struct spi_device *spi)
|
|
|
{
|
|
|
- snd_soc_unregister_codec(&spi->dev);
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
@@ -1292,15 +1292,14 @@ static int wm8900_i2c_probe(struct i2c_client *i2c,
|
|
|
|
|
|
i2c_set_clientdata(i2c, wm8900);
|
|
|
|
|
|
- ret = snd_soc_register_codec(&i2c->dev,
|
|
|
- &soc_codec_dev_wm8900, &wm8900_dai, 1);
|
|
|
+ ret = devm_snd_soc_register_component(&i2c->dev,
|
|
|
+ &soc_component_dev_wm8900, &wm8900_dai, 1);
|
|
|
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
static int wm8900_i2c_remove(struct i2c_client *client)
|
|
|
{
|
|
|
- snd_soc_unregister_codec(&client->dev);
|
|
|
return 0;
|
|
|
}
|
|
|
|