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@@ -3141,11 +3141,26 @@ static int dce_v10_0_wait_for_idle(void *handle)
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return 0;
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return 0;
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}
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}
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+static int dce_v10_0_check_soft_reset(void *handle)
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+{
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+ struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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+
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+ if (dce_v10_0_is_display_hung(adev))
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+ adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang = true;
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+ else
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+ adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang = false;
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+
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+ return 0;
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+}
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+
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static int dce_v10_0_soft_reset(void *handle)
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static int dce_v10_0_soft_reset(void *handle)
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{
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{
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u32 srbm_soft_reset = 0, tmp;
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u32 srbm_soft_reset = 0, tmp;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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+ if (!adev->ip_block_status[AMD_IP_BLOCK_TYPE_DCE].hang)
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+ return 0;
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+
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if (dce_v10_0_is_display_hung(adev))
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if (dce_v10_0_is_display_hung(adev))
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srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
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srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
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@@ -3512,6 +3527,7 @@ const struct amd_ip_funcs dce_v10_0_ip_funcs = {
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.resume = dce_v10_0_resume,
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.resume = dce_v10_0_resume,
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.is_idle = dce_v10_0_is_idle,
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.is_idle = dce_v10_0_is_idle,
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.wait_for_idle = dce_v10_0_wait_for_idle,
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.wait_for_idle = dce_v10_0_wait_for_idle,
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+ .check_soft_reset = dce_v10_0_check_soft_reset,
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.soft_reset = dce_v10_0_soft_reset,
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.soft_reset = dce_v10_0_soft_reset,
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.set_clockgating_state = dce_v10_0_set_clockgating_state,
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.set_clockgating_state = dce_v10_0_set_clockgating_state,
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.set_powergating_state = dce_v10_0_set_powergating_state,
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.set_powergating_state = dce_v10_0_set_powergating_state,
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