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@@ -8,29 +8,35 @@
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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+
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+#include <linux/clk-provider.h>
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+#include <linux/clk/davinci.h>
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+#include <linux/clkdev.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/init.h>
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-#include <linux/clk.h>
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-#include <linux/serial_8250.h>
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-#include <linux/platform_device.h>
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#include <linux/platform_data/edma.h>
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#include <linux/platform_data/gpio-davinci.h>
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+#include <linux/platform_device.h>
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+#include <linux/serial_8250.h>
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#include <asm/mach/map.h>
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+#include <mach/common.h>
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#include <mach/cputype.h>
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#include <mach/irqs.h>
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-#include "psc.h"
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#include <mach/mux.h>
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-#include <mach/time.h>
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#include <mach/serial.h>
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-#include <mach/common.h>
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+#include <mach/time.h>
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+#include "asp.h"
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#include "davinci.h"
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-#include "clock.h"
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#include "mux.h"
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-#include "asp.h"
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+
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+#ifndef CONFIG_COMMON_CLK
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+#include "clock.h"
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+#include "psc.h"
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+#endif
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#define DAVINCI_VPIF_BASE (0x01C12000)
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@@ -46,6 +52,7 @@
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#define DM646X_EMAC_CNTRL_RAM_OFFSET 0x2000
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#define DM646X_EMAC_CNTRL_RAM_SIZE 0x2000
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+#ifndef CONFIG_COMMON_CLK
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static struct pll_data pll1_data = {
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.num = 1,
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.phys_base = DAVINCI_PLL1_BASE,
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@@ -356,6 +363,7 @@ static struct clk_lookup dm646x_clks[] = {
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CLK(NULL, "vpif1", &vpif1_clk),
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CLK(NULL, NULL, NULL),
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};
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+#endif
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static struct emac_platform_data dm646x_emac_pdata = {
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.ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
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@@ -954,10 +962,49 @@ void __init dm646x_init(void)
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void __init dm646x_init_time(unsigned long ref_clk_rate,
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unsigned long aux_clkin_rate)
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{
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+#ifdef CONFIG_COMMON_CLK
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+ void __iomem *pll1, *psc;
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+ struct clk *clk;
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+
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+ clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, ref_clk_rate);
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+ clk_register_fixed_rate(NULL, "aux_clkin", NULL, 0, aux_clkin_rate);
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+
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+ pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
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+ dm646x_pll1_init(NULL, pll1, NULL);
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+
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+ psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
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+ dm646x_psc_init(NULL, psc);
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+
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+ clk = clk_get(NULL, "timer0");
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+
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+ davinci_timer_init(clk);
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+#else
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ref_clk.rate = ref_clk_rate;
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aux_clkin.rate = aux_clkin_rate;
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davinci_clk_init(dm646x_clks);
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davinci_timer_init(&timer0_clk);
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+#endif
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+}
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+
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+static struct resource dm646x_pll2_resources[] = {
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+ {
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+ .start = DAVINCI_PLL2_BASE,
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+ .end = DAVINCI_PLL2_BASE + SZ_1K - 1,
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+ .flags = IORESOURCE_MEM,
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+ },
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+};
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+
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+static struct platform_device dm646x_pll2_device = {
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+ .name = "dm646x-pll2",
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+ .id = -1,
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+ .resource = dm646x_pll2_resources,
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+ .num_resources = ARRAY_SIZE(dm646x_pll2_resources),
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+};
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+
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+void __init dm646x_register_clocks(void)
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+{
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+ /* PLL1 and PSC are registered in dm646x_init_time() */
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+ platform_device_register(&dm646x_pll2_device);
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}
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static int __init dm646x_init_devices(void)
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