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@@ -31,6 +31,7 @@
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#include <linux/acpi.h>
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#include <linux/module.h>
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#include <linux/syscore_ops.h>
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+#include <linux/irqdomain.h>
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#include <linux/msi.h>
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#include <linux/htirq.h>
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#include <linux/freezer.h>
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@@ -62,6 +63,16 @@
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#define __apicdebuginit(type) static type __init
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+#define for_each_ioapic(idx) \
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+ for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
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+#define for_each_ioapic_reverse(idx) \
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+ for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
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+#define for_each_pin(idx, pin) \
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+ for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
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+#define for_each_ioapic_pin(idx, pin) \
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+ for_each_ioapic((idx)) \
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+ for_each_pin((idx), (pin))
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+
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#define for_each_irq_pin(entry, head) \
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for (entry = head; entry; entry = entry->next)
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@@ -73,6 +84,17 @@ int sis_apic_bug = -1;
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static DEFINE_RAW_SPINLOCK(ioapic_lock);
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static DEFINE_RAW_SPINLOCK(vector_lock);
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+static DEFINE_MUTEX(ioapic_mutex);
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+static unsigned int ioapic_dynirq_base;
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+static int ioapic_initialized;
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+
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+struct mp_pin_info {
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+ int trigger;
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+ int polarity;
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+ int node;
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+ int set;
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+ u32 count;
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+};
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static struct ioapic {
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/*
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@@ -87,7 +109,9 @@ static struct ioapic {
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struct mpc_ioapic mp_config;
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/* IO APIC gsi routing info */
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struct mp_ioapic_gsi gsi_config;
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- DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
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+ struct ioapic_domain_cfg irqdomain_cfg;
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+ struct irq_domain *irqdomain;
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+ struct mp_pin_info *pin_info;
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} ioapics[MAX_IO_APICS];
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#define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
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@@ -107,6 +131,41 @@ struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
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return &ioapics[ioapic_idx].gsi_config;
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}
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+static inline int mp_ioapic_pin_count(int ioapic)
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+{
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+ struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
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+
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+ return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
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+}
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+
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+u32 mp_pin_to_gsi(int ioapic, int pin)
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+{
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+ return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
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+}
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+
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+/*
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+ * Initialize all legacy IRQs and all pins on the first IOAPIC
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+ * if we have legacy interrupt controller. Kernel boot option "pirq="
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+ * may rely on non-legacy pins on the first IOAPIC.
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+ */
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+static inline int mp_init_irq_at_boot(int ioapic, int irq)
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+{
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+ if (!nr_legacy_irqs())
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+ return 0;
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+
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+ return ioapic == 0 || (irq >= 0 && irq < nr_legacy_irqs());
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+}
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+
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+static inline struct mp_pin_info *mp_pin_info(int ioapic_idx, int pin)
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+{
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+ return ioapics[ioapic_idx].pin_info + pin;
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+}
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+
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+static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
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+{
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+ return ioapics[ioapic].irqdomain;
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+}
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+
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int nr_ioapics;
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/* The one past the highest gsi number used */
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@@ -118,9 +177,6 @@ struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
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/* # of MP IRQ source entries */
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int mp_irq_entries;
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-/* GSI interrupts */
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-static int nr_irqs_gsi = NR_IRQS_LEGACY;
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-
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#ifdef CONFIG_EISA
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int mp_bus_id_to_type[MAX_MP_BUSSES];
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#endif
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@@ -149,8 +205,7 @@ static int __init parse_noapic(char *str)
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}
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early_param("noapic", parse_noapic);
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-static int io_apic_setup_irq_pin(unsigned int irq, int node,
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- struct io_apic_irq_attr *attr);
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+static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node);
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/* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
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void mp_save_irq(struct mpc_intsrc *m)
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@@ -182,19 +237,15 @@ static struct irq_pin_list *alloc_irq_pin_list(int node)
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return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
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}
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-
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-/* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
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-static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
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-
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int __init arch_early_irq_init(void)
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{
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struct irq_cfg *cfg;
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- int count, node, i;
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+ int i, node = cpu_to_node(0);
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- if (!legacy_pic->nr_legacy_irqs)
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+ if (!nr_legacy_irqs())
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io_apic_irqs = ~0UL;
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- for (i = 0; i < nr_ioapics; i++) {
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+ for_each_ioapic(i) {
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ioapics[i].saved_registers =
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kzalloc(sizeof(struct IO_APIC_route_entry) *
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ioapics[i].nr_registers, GFP_KERNEL);
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@@ -202,28 +253,20 @@ int __init arch_early_irq_init(void)
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pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
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}
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- cfg = irq_cfgx;
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- count = ARRAY_SIZE(irq_cfgx);
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- node = cpu_to_node(0);
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-
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- for (i = 0; i < count; i++) {
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- irq_set_chip_data(i, &cfg[i]);
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- zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
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- zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
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- /*
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- * For legacy IRQ's, start with assigning irq0 to irq15 to
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- * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
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- */
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- if (i < legacy_pic->nr_legacy_irqs) {
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- cfg[i].vector = IRQ0_VECTOR + i;
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- cpumask_setall(cfg[i].domain);
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- }
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+ /*
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+ * For legacy IRQ's, start with assigning irq0 to irq15 to
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+ * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's.
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+ */
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+ for (i = 0; i < nr_legacy_irqs(); i++) {
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+ cfg = alloc_irq_and_cfg_at(i, node);
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+ cfg->vector = IRQ0_VECTOR + i;
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+ cpumask_setall(cfg->domain);
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}
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return 0;
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}
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-static struct irq_cfg *irq_cfg(unsigned int irq)
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+static inline struct irq_cfg *irq_cfg(unsigned int irq)
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{
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return irq_get_chip_data(irq);
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}
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@@ -265,7 +308,7 @@ static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
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if (res < 0) {
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if (res != -EEXIST)
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return NULL;
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- cfg = irq_get_chip_data(at);
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+ cfg = irq_cfg(at);
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if (cfg)
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return cfg;
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}
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@@ -425,6 +468,21 @@ static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pi
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return 0;
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}
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+static void __remove_pin_from_irq(struct irq_cfg *cfg, int apic, int pin)
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+{
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+ struct irq_pin_list **last, *entry;
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+
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+ last = &cfg->irq_2_pin;
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+ for_each_irq_pin(entry, cfg->irq_2_pin)
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+ if (entry->apic == apic && entry->pin == pin) {
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+ *last = entry->next;
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+ kfree(entry);
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+ return;
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+ } else {
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+ last = &entry->next;
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+ }
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+}
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+
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static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
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{
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if (__add_pin_to_irq_node(cfg, node, apic, pin))
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@@ -627,9 +685,8 @@ static void clear_IO_APIC (void)
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{
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int apic, pin;
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- for (apic = 0; apic < nr_ioapics; apic++)
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- for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
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- clear_IO_APIC_pin(apic, pin);
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+ for_each_ioapic_pin(apic, pin)
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+ clear_IO_APIC_pin(apic, pin);
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}
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#ifdef CONFIG_X86_32
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@@ -678,13 +735,13 @@ int save_ioapic_entries(void)
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int apic, pin;
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int err = 0;
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- for (apic = 0; apic < nr_ioapics; apic++) {
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+ for_each_ioapic(apic) {
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if (!ioapics[apic].saved_registers) {
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err = -ENOMEM;
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continue;
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}
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- for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
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+ for_each_pin(apic, pin)
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ioapics[apic].saved_registers[pin] =
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ioapic_read_entry(apic, pin);
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}
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@@ -699,11 +756,11 @@ void mask_ioapic_entries(void)
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{
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int apic, pin;
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- for (apic = 0; apic < nr_ioapics; apic++) {
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+ for_each_ioapic(apic) {
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if (!ioapics[apic].saved_registers)
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continue;
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- for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
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+ for_each_pin(apic, pin) {
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struct IO_APIC_route_entry entry;
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entry = ioapics[apic].saved_registers[pin];
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@@ -722,11 +779,11 @@ int restore_ioapic_entries(void)
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{
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int apic, pin;
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- for (apic = 0; apic < nr_ioapics; apic++) {
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+ for_each_ioapic(apic) {
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if (!ioapics[apic].saved_registers)
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continue;
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- for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
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+ for_each_pin(apic, pin)
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ioapic_write_entry(apic, pin,
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ioapics[apic].saved_registers[pin]);
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}
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@@ -785,7 +842,7 @@ static int __init find_isa_irq_apic(int irq, int type)
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if (i < mp_irq_entries) {
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int ioapic_idx;
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- for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
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+ for_each_ioapic(ioapic_idx)
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if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
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return ioapic_idx;
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}
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@@ -799,7 +856,7 @@ static int __init find_isa_irq_apic(int irq, int type)
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*/
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static int EISA_ELCR(unsigned int irq)
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{
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- if (irq < legacy_pic->nr_legacy_irqs) {
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+ if (irq < nr_legacy_irqs()) {
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unsigned int port = 0x4d0 + (irq >> 3);
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return (inb(port) >> (irq & 7)) & 1;
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}
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@@ -939,29 +996,101 @@ static int irq_trigger(int idx)
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return trigger;
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}
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-static int pin_2_irq(int idx, int apic, int pin)
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+static int alloc_irq_from_domain(struct irq_domain *domain, u32 gsi, int pin)
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+{
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+ int irq = -1;
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+ int ioapic = (int)(long)domain->host_data;
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+ int type = ioapics[ioapic].irqdomain_cfg.type;
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+
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+ switch (type) {
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+ case IOAPIC_DOMAIN_LEGACY:
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+ /*
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+ * Dynamically allocate IRQ number for non-ISA IRQs in the first 16
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+ * GSIs on some weird platforms.
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+ */
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+ if (gsi < nr_legacy_irqs())
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+ irq = irq_create_mapping(domain, pin);
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+ else if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0)
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+ irq = gsi;
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+ break;
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+ case IOAPIC_DOMAIN_STRICT:
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+ if (irq_create_strict_mappings(domain, gsi, pin, 1) == 0)
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+ irq = gsi;
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+ break;
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+ case IOAPIC_DOMAIN_DYNAMIC:
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+ irq = irq_create_mapping(domain, pin);
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+ break;
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+ default:
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+ WARN(1, "ioapic: unknown irqdomain type %d\n", type);
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+ break;
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+ }
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+
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+ return irq > 0 ? irq : -1;
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+}
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+
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+static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
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+ unsigned int flags)
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{
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int irq;
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- int bus = mp_irqs[idx].srcbus;
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- struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
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+ struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
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+ struct mp_pin_info *info = mp_pin_info(ioapic, pin);
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+
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+ if (!domain)
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+ return -1;
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+
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+ mutex_lock(&ioapic_mutex);
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/*
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- * Debugging check, we are in big trouble if this message pops up!
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+ * Don't use irqdomain to manage ISA IRQs because there may be
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+ * multiple IOAPIC pins sharing the same ISA IRQ number and
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+ * irqdomain only supports 1:1 mapping between IOAPIC pin and
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+ * IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are used
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+ * for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
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+ * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are
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+ * available, and some BIOSes may use MP Interrupt Source records
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+ * to override IRQ numbers for PIRQs instead of reprogramming
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+ * the interrupt routing logic. Thus there may be multiple pins
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+ * sharing the same legacy IRQ number when ACPI is disabled.
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*/
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- if (mp_irqs[idx].dstirq != pin)
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- pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
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-
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- if (test_bit(bus, mp_bus_not_pci)) {
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+ if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
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irq = mp_irqs[idx].srcbusirq;
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+ if (flags & IOAPIC_MAP_ALLOC) {
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+ if (info->count == 0 &&
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+ mp_irqdomain_map(domain, irq, pin) != 0)
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+ irq = -1;
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+
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+ /* special handling for timer IRQ0 */
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+ if (irq == 0)
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+ info->count++;
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+ }
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} else {
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- u32 gsi = gsi_cfg->gsi_base + pin;
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+ irq = irq_find_mapping(domain, pin);
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+ if (irq <= 0 && (flags & IOAPIC_MAP_ALLOC))
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+ irq = alloc_irq_from_domain(domain, gsi, pin);
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+ }
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- if (gsi >= NR_IRQS_LEGACY)
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- irq = gsi;
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- else
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- irq = gsi_top + gsi;
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+ if (flags & IOAPIC_MAP_ALLOC) {
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+ if (irq > 0)
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+ info->count++;
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+ else if (info->count == 0)
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+ info->set = 0;
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}
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+ mutex_unlock(&ioapic_mutex);
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+
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|
+ return irq > 0 ? irq : -1;
|
|
|
+}
|
|
|
+
|
|
|
+static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
|
|
|
+{
|
|
|
+ u32 gsi = mp_pin_to_gsi(ioapic, pin);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Debugging check, we are in big trouble if this message pops up!
|
|
|
+ */
|
|
|
+ if (mp_irqs[idx].dstirq != pin)
|
|
|
+ pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
|
|
|
+
|
|
|
#ifdef CONFIG_X86_32
|
|
|
/*
|
|
|
* PCI IRQ command line redirection. Yes, limits are hardcoded.
|
|
|
@@ -972,16 +1101,58 @@ static int pin_2_irq(int idx, int apic, int pin)
|
|
|
apic_printk(APIC_VERBOSE, KERN_DEBUG
|
|
|
"disabling PIRQ%d\n", pin-16);
|
|
|
} else {
|
|
|
- irq = pirq_entries[pin-16];
|
|
|
+ int irq = pirq_entries[pin-16];
|
|
|
apic_printk(APIC_VERBOSE, KERN_DEBUG
|
|
|
"using PIRQ%d -> IRQ %d\n",
|
|
|
pin-16, irq);
|
|
|
+ return irq;
|
|
|
}
|
|
|
}
|
|
|
}
|
|
|
#endif
|
|
|
|
|
|
- return irq;
|
|
|
+ return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags);
|
|
|
+}
|
|
|
+
|
|
|
+int mp_map_gsi_to_irq(u32 gsi, unsigned int flags)
|
|
|
+{
|
|
|
+ int ioapic, pin, idx;
|
|
|
+
|
|
|
+ ioapic = mp_find_ioapic(gsi);
|
|
|
+ if (ioapic < 0)
|
|
|
+ return -1;
|
|
|
+
|
|
|
+ pin = mp_find_ioapic_pin(ioapic, gsi);
|
|
|
+ idx = find_irq_entry(ioapic, pin, mp_INT);
|
|
|
+ if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
|
|
|
+ return -1;
|
|
|
+
|
|
|
+ return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags);
|
|
|
+}
|
|
|
+
|
|
|
+void mp_unmap_irq(int irq)
|
|
|
+{
|
|
|
+ struct irq_data *data = irq_get_irq_data(irq);
|
|
|
+ struct mp_pin_info *info;
|
|
|
+ int ioapic, pin;
|
|
|
+
|
|
|
+ if (!data || !data->domain)
|
|
|
+ return;
|
|
|
+
|
|
|
+ ioapic = (int)(long)data->domain->host_data;
|
|
|
+ pin = (int)data->hwirq;
|
|
|
+ info = mp_pin_info(ioapic, pin);
|
|
|
+
|
|
|
+ mutex_lock(&ioapic_mutex);
|
|
|
+ if (--info->count == 0) {
|
|
|
+ info->set = 0;
|
|
|
+ if (irq < nr_legacy_irqs() &&
|
|
|
+ ioapics[ioapic].irqdomain_cfg.type == IOAPIC_DOMAIN_LEGACY)
|
|
|
+ mp_irqdomain_unmap(data->domain, irq);
|
|
|
+ else
|
|
|
+ irq_dispose_mapping(irq);
|
|
|
+ }
|
|
|
+ mutex_unlock(&ioapic_mutex);
|
|
|
}
|
|
|
|
|
|
/*
|
|
|
@@ -991,7 +1162,7 @@ static int pin_2_irq(int idx, int apic, int pin)
|
|
|
int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
|
|
|
struct io_apic_irq_attr *irq_attr)
|
|
|
{
|
|
|
- int ioapic_idx, i, best_guess = -1;
|
|
|
+ int irq, i, best_ioapic = -1, best_idx = -1;
|
|
|
|
|
|
apic_printk(APIC_DEBUG,
|
|
|
"querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
|
|
|
@@ -1001,44 +1172,56 @@ int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
|
|
|
"PCI BIOS passed nonexistent PCI bus %d!\n", bus);
|
|
|
return -1;
|
|
|
}
|
|
|
+
|
|
|
for (i = 0; i < mp_irq_entries; i++) {
|
|
|
int lbus = mp_irqs[i].srcbus;
|
|
|
+ int ioapic_idx, found = 0;
|
|
|
|
|
|
- for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
|
|
|
+ if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
|
|
|
+ slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
|
|
|
+ continue;
|
|
|
+
|
|
|
+ for_each_ioapic(ioapic_idx)
|
|
|
if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
|
|
|
- mp_irqs[i].dstapic == MP_APIC_ALL)
|
|
|
+ mp_irqs[i].dstapic == MP_APIC_ALL) {
|
|
|
+ found = 1;
|
|
|
break;
|
|
|
+ }
|
|
|
+ if (!found)
|
|
|
+ continue;
|
|
|
|
|
|
- if (!test_bit(lbus, mp_bus_not_pci) &&
|
|
|
- !mp_irqs[i].irqtype &&
|
|
|
- (bus == lbus) &&
|
|
|
- (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
|
|
|
- int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
|
|
|
+ /* Skip ISA IRQs */
|
|
|
+ irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
|
|
|
+ if (irq > 0 && !IO_APIC_IRQ(irq))
|
|
|
+ continue;
|
|
|
|
|
|
- if (!(ioapic_idx || IO_APIC_IRQ(irq)))
|
|
|
- continue;
|
|
|
+ if (pin == (mp_irqs[i].srcbusirq & 3)) {
|
|
|
+ best_idx = i;
|
|
|
+ best_ioapic = ioapic_idx;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
|
|
|
- if (pin == (mp_irqs[i].srcbusirq & 3)) {
|
|
|
- set_io_apic_irq_attr(irq_attr, ioapic_idx,
|
|
|
- mp_irqs[i].dstirq,
|
|
|
- irq_trigger(i),
|
|
|
- irq_polarity(i));
|
|
|
- return irq;
|
|
|
- }
|
|
|
- /*
|
|
|
- * Use the first all-but-pin matching entry as a
|
|
|
- * best-guess fuzzy result for broken mptables.
|
|
|
- */
|
|
|
- if (best_guess < 0) {
|
|
|
- set_io_apic_irq_attr(irq_attr, ioapic_idx,
|
|
|
- mp_irqs[i].dstirq,
|
|
|
- irq_trigger(i),
|
|
|
- irq_polarity(i));
|
|
|
- best_guess = irq;
|
|
|
- }
|
|
|
+ /*
|
|
|
+ * Use the first all-but-pin matching entry as a
|
|
|
+ * best-guess fuzzy result for broken mptables.
|
|
|
+ */
|
|
|
+ if (best_idx < 0) {
|
|
|
+ best_idx = i;
|
|
|
+ best_ioapic = ioapic_idx;
|
|
|
}
|
|
|
}
|
|
|
- return best_guess;
|
|
|
+ if (best_idx < 0)
|
|
|
+ return -1;
|
|
|
+
|
|
|
+out:
|
|
|
+ irq = pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
|
|
|
+ IOAPIC_MAP_ALLOC);
|
|
|
+ if (irq > 0)
|
|
|
+ set_io_apic_irq_attr(irq_attr, best_ioapic,
|
|
|
+ mp_irqs[best_idx].dstirq,
|
|
|
+ irq_trigger(best_idx),
|
|
|
+ irq_polarity(best_idx));
|
|
|
+ return irq;
|
|
|
}
|
|
|
EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
|
|
|
|
|
|
@@ -1198,7 +1381,7 @@ void __setup_vector_irq(int cpu)
|
|
|
raw_spin_lock(&vector_lock);
|
|
|
/* Mark the inuse vectors */
|
|
|
for_each_active_irq(irq) {
|
|
|
- cfg = irq_get_chip_data(irq);
|
|
|
+ cfg = irq_cfg(irq);
|
|
|
if (!cfg)
|
|
|
continue;
|
|
|
|
|
|
@@ -1227,12 +1410,10 @@ static inline int IO_APIC_irq_trigger(int irq)
|
|
|
{
|
|
|
int apic, idx, pin;
|
|
|
|
|
|
- for (apic = 0; apic < nr_ioapics; apic++) {
|
|
|
- for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
|
|
|
- idx = find_irq_entry(apic, pin, mp_INT);
|
|
|
- if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
|
|
|
- return irq_trigger(idx);
|
|
|
- }
|
|
|
+ for_each_ioapic_pin(apic, pin) {
|
|
|
+ idx = find_irq_entry(apic, pin, mp_INT);
|
|
|
+ if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0)))
|
|
|
+ return irq_trigger(idx);
|
|
|
}
|
|
|
/*
|
|
|
* nonexistent IRQs are edge default
|
|
|
@@ -1330,95 +1511,29 @@ static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
|
|
|
}
|
|
|
|
|
|
ioapic_register_intr(irq, cfg, attr->trigger);
|
|
|
- if (irq < legacy_pic->nr_legacy_irqs)
|
|
|
+ if (irq < nr_legacy_irqs())
|
|
|
legacy_pic->mask(irq);
|
|
|
|
|
|
ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
|
|
|
}
|
|
|
|
|
|
-static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
|
|
|
-{
|
|
|
- if (idx != -1)
|
|
|
- return false;
|
|
|
-
|
|
|
- apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
|
|
|
- mpc_ioapic_id(ioapic_idx), pin);
|
|
|
- return true;
|
|
|
-}
|
|
|
-
|
|
|
-static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
|
|
|
-{
|
|
|
- int idx, node = cpu_to_node(0);
|
|
|
- struct io_apic_irq_attr attr;
|
|
|
- unsigned int pin, irq;
|
|
|
-
|
|
|
- for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
|
|
|
- idx = find_irq_entry(ioapic_idx, pin, mp_INT);
|
|
|
- if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
|
|
|
- continue;
|
|
|
-
|
|
|
- irq = pin_2_irq(idx, ioapic_idx, pin);
|
|
|
-
|
|
|
- if ((ioapic_idx > 0) && (irq > 16))
|
|
|
- continue;
|
|
|
-
|
|
|
- /*
|
|
|
- * Skip the timer IRQ if there's a quirk handler
|
|
|
- * installed and if it returns 1:
|
|
|
- */
|
|
|
- if (apic->multi_timer_check &&
|
|
|
- apic->multi_timer_check(ioapic_idx, irq))
|
|
|
- continue;
|
|
|
-
|
|
|
- set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
|
|
|
- irq_polarity(idx));
|
|
|
-
|
|
|
- io_apic_setup_irq_pin(irq, node, &attr);
|
|
|
- }
|
|
|
-}
|
|
|
-
|
|
|
static void __init setup_IO_APIC_irqs(void)
|
|
|
{
|
|
|
- unsigned int ioapic_idx;
|
|
|
+ unsigned int ioapic, pin;
|
|
|
+ int idx;
|
|
|
|
|
|
apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
|
|
|
|
|
|
- for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
|
|
|
- __io_apic_setup_irqs(ioapic_idx);
|
|
|
-}
|
|
|
-
|
|
|
-/*
|
|
|
- * for the gsit that is not in first ioapic
|
|
|
- * but could not use acpi_register_gsi()
|
|
|
- * like some special sci in IBM x3330
|
|
|
- */
|
|
|
-void setup_IO_APIC_irq_extra(u32 gsi)
|
|
|
-{
|
|
|
- int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
|
|
|
- struct io_apic_irq_attr attr;
|
|
|
-
|
|
|
- /*
|
|
|
- * Convert 'gsi' to 'ioapic.pin'.
|
|
|
- */
|
|
|
- ioapic_idx = mp_find_ioapic(gsi);
|
|
|
- if (ioapic_idx < 0)
|
|
|
- return;
|
|
|
-
|
|
|
- pin = mp_find_ioapic_pin(ioapic_idx, gsi);
|
|
|
- idx = find_irq_entry(ioapic_idx, pin, mp_INT);
|
|
|
- if (idx == -1)
|
|
|
- return;
|
|
|
-
|
|
|
- irq = pin_2_irq(idx, ioapic_idx, pin);
|
|
|
-
|
|
|
- /* Only handle the non legacy irqs on secondary ioapics */
|
|
|
- if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
|
|
|
- return;
|
|
|
-
|
|
|
- set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
|
|
|
- irq_polarity(idx));
|
|
|
-
|
|
|
- io_apic_setup_irq_pin_once(irq, node, &attr);
|
|
|
+ for_each_ioapic_pin(ioapic, pin) {
|
|
|
+ idx = find_irq_entry(ioapic, pin, mp_INT);
|
|
|
+ if (idx < 0)
|
|
|
+ apic_printk(APIC_VERBOSE,
|
|
|
+ KERN_DEBUG " apic %d pin %d not connected\n",
|
|
|
+ mpc_ioapic_id(ioapic), pin);
|
|
|
+ else
|
|
|
+ pin_2_irq(idx, ioapic, pin,
|
|
|
+ ioapic ? 0 : IOAPIC_MAP_ALLOC);
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
/*
|
|
|
@@ -1586,7 +1701,7 @@ __apicdebuginit(void) print_IO_APICs(void)
|
|
|
struct irq_chip *chip;
|
|
|
|
|
|
printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
|
|
|
- for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
|
|
|
+ for_each_ioapic(ioapic_idx)
|
|
|
printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
|
|
|
mpc_ioapic_id(ioapic_idx),
|
|
|
ioapics[ioapic_idx].nr_registers);
|
|
|
@@ -1597,7 +1712,7 @@ __apicdebuginit(void) print_IO_APICs(void)
|
|
|
*/
|
|
|
printk(KERN_INFO "testing the IO APIC.......................\n");
|
|
|
|
|
|
- for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
|
|
|
+ for_each_ioapic(ioapic_idx)
|
|
|
print_IO_APIC(ioapic_idx);
|
|
|
|
|
|
printk(KERN_DEBUG "IRQ to pin mappings:\n");
|
|
|
@@ -1608,7 +1723,7 @@ __apicdebuginit(void) print_IO_APICs(void)
|
|
|
if (chip != &ioapic_chip)
|
|
|
continue;
|
|
|
|
|
|
- cfg = irq_get_chip_data(irq);
|
|
|
+ cfg = irq_cfg(irq);
|
|
|
if (!cfg)
|
|
|
continue;
|
|
|
entry = cfg->irq_2_pin;
|
|
|
@@ -1758,7 +1873,7 @@ __apicdebuginit(void) print_PIC(void)
|
|
|
unsigned int v;
|
|
|
unsigned long flags;
|
|
|
|
|
|
- if (!legacy_pic->nr_legacy_irqs)
|
|
|
+ if (!nr_legacy_irqs())
|
|
|
return;
|
|
|
|
|
|
printk(KERN_DEBUG "\nprinting PIC contents\n");
|
|
|
@@ -1828,26 +1943,22 @@ static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
|
|
|
void __init enable_IO_APIC(void)
|
|
|
{
|
|
|
int i8259_apic, i8259_pin;
|
|
|
- int apic;
|
|
|
+ int apic, pin;
|
|
|
|
|
|
- if (!legacy_pic->nr_legacy_irqs)
|
|
|
+ if (!nr_legacy_irqs())
|
|
|
return;
|
|
|
|
|
|
- for(apic = 0; apic < nr_ioapics; apic++) {
|
|
|
- int pin;
|
|
|
+ for_each_ioapic_pin(apic, pin) {
|
|
|
/* See if any of the pins is in ExtINT mode */
|
|
|
- for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
|
|
|
- struct IO_APIC_route_entry entry;
|
|
|
- entry = ioapic_read_entry(apic, pin);
|
|
|
+ struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
|
|
|
|
|
|
- /* If the interrupt line is enabled and in ExtInt mode
|
|
|
- * I have found the pin where the i8259 is connected.
|
|
|
- */
|
|
|
- if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
|
|
|
- ioapic_i8259.apic = apic;
|
|
|
- ioapic_i8259.pin = pin;
|
|
|
- goto found_i8259;
|
|
|
- }
|
|
|
+ /* If the interrupt line is enabled and in ExtInt mode
|
|
|
+ * I have found the pin where the i8259 is connected.
|
|
|
+ */
|
|
|
+ if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
|
|
|
+ ioapic_i8259.apic = apic;
|
|
|
+ ioapic_i8259.pin = pin;
|
|
|
+ goto found_i8259;
|
|
|
}
|
|
|
}
|
|
|
found_i8259:
|
|
|
@@ -1919,7 +2030,7 @@ void disable_IO_APIC(void)
|
|
|
*/
|
|
|
clear_IO_APIC();
|
|
|
|
|
|
- if (!legacy_pic->nr_legacy_irqs)
|
|
|
+ if (!nr_legacy_irqs())
|
|
|
return;
|
|
|
|
|
|
x86_io_apic_ops.disable();
|
|
|
@@ -1950,7 +2061,7 @@ void __init setup_ioapic_ids_from_mpc_nocheck(void)
|
|
|
/*
|
|
|
* Set the IOAPIC ID to the value stored in the MPC table.
|
|
|
*/
|
|
|
- for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
|
|
|
+ for_each_ioapic(ioapic_idx) {
|
|
|
/* Read the register 0 value */
|
|
|
raw_spin_lock_irqsave(&ioapic_lock, flags);
|
|
|
reg_00.raw = io_apic_read(ioapic_idx, 0);
|
|
|
@@ -2123,7 +2234,7 @@ static unsigned int startup_ioapic_irq(struct irq_data *data)
|
|
|
unsigned long flags;
|
|
|
|
|
|
raw_spin_lock_irqsave(&ioapic_lock, flags);
|
|
|
- if (irq < legacy_pic->nr_legacy_irqs) {
|
|
|
+ if (irq < nr_legacy_irqs()) {
|
|
|
legacy_pic->mask(irq);
|
|
|
if (legacy_pic->irq_pending(irq))
|
|
|
was_pending = 1;
|
|
|
@@ -2225,7 +2336,7 @@ asmlinkage __visible void smp_irq_move_cleanup_interrupt(void)
|
|
|
apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
|
|
|
goto unlock;
|
|
|
}
|
|
|
- __this_cpu_write(vector_irq[vector], -1);
|
|
|
+ __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
|
|
|
unlock:
|
|
|
raw_spin_unlock(&desc->lock);
|
|
|
}
|
|
|
@@ -2253,7 +2364,7 @@ static void irq_complete_move(struct irq_cfg *cfg)
|
|
|
|
|
|
void irq_force_complete_move(int irq)
|
|
|
{
|
|
|
- struct irq_cfg *cfg = irq_get_chip_data(irq);
|
|
|
+ struct irq_cfg *cfg = irq_cfg(irq);
|
|
|
|
|
|
if (!cfg)
|
|
|
return;
|
|
|
@@ -2514,26 +2625,15 @@ static inline void init_IO_APIC_traps(void)
|
|
|
struct irq_cfg *cfg;
|
|
|
unsigned int irq;
|
|
|
|
|
|
- /*
|
|
|
- * NOTE! The local APIC isn't very good at handling
|
|
|
- * multiple interrupts at the same interrupt level.
|
|
|
- * As the interrupt level is determined by taking the
|
|
|
- * vector number and shifting that right by 4, we
|
|
|
- * want to spread these out a bit so that they don't
|
|
|
- * all fall in the same interrupt level.
|
|
|
- *
|
|
|
- * Also, we've got to be careful not to trash gate
|
|
|
- * 0x80, because int 0x80 is hm, kind of importantish. ;)
|
|
|
- */
|
|
|
for_each_active_irq(irq) {
|
|
|
- cfg = irq_get_chip_data(irq);
|
|
|
+ cfg = irq_cfg(irq);
|
|
|
if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
|
|
|
/*
|
|
|
* Hmm.. We don't have an entry for this,
|
|
|
* so default to an old-fashioned 8259
|
|
|
* interrupt if we can..
|
|
|
*/
|
|
|
- if (irq < legacy_pic->nr_legacy_irqs)
|
|
|
+ if (irq < nr_legacy_irqs())
|
|
|
legacy_pic->make_irq(irq);
|
|
|
else
|
|
|
/* Strange. Oh, well.. */
|
|
|
@@ -2649,8 +2749,6 @@ static int __init disable_timer_pin_setup(char *arg)
|
|
|
}
|
|
|
early_param("disable_timer_pin_1", disable_timer_pin_setup);
|
|
|
|
|
|
-int timer_through_8259 __initdata;
|
|
|
-
|
|
|
/*
|
|
|
* This code may look a bit paranoid, but it's supposed to cooperate with
|
|
|
* a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
|
|
|
@@ -2661,7 +2759,7 @@ int timer_through_8259 __initdata;
|
|
|
*/
|
|
|
static inline void __init check_timer(void)
|
|
|
{
|
|
|
- struct irq_cfg *cfg = irq_get_chip_data(0);
|
|
|
+ struct irq_cfg *cfg = irq_cfg(0);
|
|
|
int node = cpu_to_node(0);
|
|
|
int apic1, pin1, apic2, pin2;
|
|
|
unsigned long flags;
|
|
|
@@ -2755,7 +2853,6 @@ static inline void __init check_timer(void)
|
|
|
legacy_pic->unmask(0);
|
|
|
if (timer_irq_works()) {
|
|
|
apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
|
|
|
- timer_through_8259 = 1;
|
|
|
goto out;
|
|
|
}
|
|
|
/*
|
|
|
@@ -2827,15 +2924,54 @@ out:
|
|
|
*/
|
|
|
#define PIC_IRQS (1UL << PIC_CASCADE_IR)
|
|
|
|
|
|
+static int mp_irqdomain_create(int ioapic)
|
|
|
+{
|
|
|
+ size_t size;
|
|
|
+ int hwirqs = mp_ioapic_pin_count(ioapic);
|
|
|
+ struct ioapic *ip = &ioapics[ioapic];
|
|
|
+ struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
|
|
|
+ struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
|
|
|
+
|
|
|
+ size = sizeof(struct mp_pin_info) * mp_ioapic_pin_count(ioapic);
|
|
|
+ ip->pin_info = kzalloc(size, GFP_KERNEL);
|
|
|
+ if (!ip->pin_info)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ if (cfg->type == IOAPIC_DOMAIN_INVALID)
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
|
|
|
+ (void *)(long)ioapic);
|
|
|
+ if(!ip->irqdomain) {
|
|
|
+ kfree(ip->pin_info);
|
|
|
+ ip->pin_info = NULL;
|
|
|
+ return -ENOMEM;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
|
|
|
+ cfg->type == IOAPIC_DOMAIN_STRICT)
|
|
|
+ ioapic_dynirq_base = max(ioapic_dynirq_base,
|
|
|
+ gsi_cfg->gsi_end + 1);
|
|
|
+
|
|
|
+ if (gsi_cfg->gsi_base == 0)
|
|
|
+ irq_set_default_host(ip->irqdomain);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
void __init setup_IO_APIC(void)
|
|
|
{
|
|
|
+ int ioapic;
|
|
|
|
|
|
/*
|
|
|
* calling enable_IO_APIC() is moved to setup_local_APIC for BP
|
|
|
*/
|
|
|
- io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
|
|
|
+ io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
|
|
|
|
|
|
apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
|
|
|
+ for_each_ioapic(ioapic)
|
|
|
+ BUG_ON(mp_irqdomain_create(ioapic));
|
|
|
+
|
|
|
/*
|
|
|
* Set up IO-APIC IRQ routing.
|
|
|
*/
|
|
|
@@ -2844,8 +2980,10 @@ void __init setup_IO_APIC(void)
|
|
|
sync_Arb_IDs();
|
|
|
setup_IO_APIC_irqs();
|
|
|
init_IO_APIC_traps();
|
|
|
- if (legacy_pic->nr_legacy_irqs)
|
|
|
+ if (nr_legacy_irqs())
|
|
|
check_timer();
|
|
|
+
|
|
|
+ ioapic_initialized = 1;
|
|
|
}
|
|
|
|
|
|
/*
|
|
|
@@ -2880,7 +3018,7 @@ static void ioapic_resume(void)
|
|
|
{
|
|
|
int ioapic_idx;
|
|
|
|
|
|
- for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
|
|
|
+ for_each_ioapic_reverse(ioapic_idx)
|
|
|
resume_ioapic_id(ioapic_idx);
|
|
|
|
|
|
restore_ioapic_entries();
|
|
|
@@ -2926,7 +3064,7 @@ int arch_setup_hwirq(unsigned int irq, int node)
|
|
|
|
|
|
void arch_teardown_hwirq(unsigned int irq)
|
|
|
{
|
|
|
- struct irq_cfg *cfg = irq_get_chip_data(irq);
|
|
|
+ struct irq_cfg *cfg = irq_cfg(irq);
|
|
|
unsigned long flags;
|
|
|
|
|
|
free_remapped_irq(irq);
|
|
|
@@ -3053,7 +3191,7 @@ int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc,
|
|
|
if (!irq_offset)
|
|
|
write_msi_msg(irq, &msg);
|
|
|
|
|
|
- setup_remapped_irq(irq, irq_get_chip_data(irq), chip);
|
|
|
+ setup_remapped_irq(irq, irq_cfg(irq), chip);
|
|
|
|
|
|
irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
|
|
|
|
|
|
@@ -3192,7 +3330,7 @@ int default_setup_hpet_msi(unsigned int irq, unsigned int id)
|
|
|
|
|
|
hpet_msi_write(irq_get_handler_data(irq), &msg);
|
|
|
irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
|
|
|
- setup_remapped_irq(irq, irq_get_chip_data(irq), chip);
|
|
|
+ setup_remapped_irq(irq, irq_cfg(irq), chip);
|
|
|
|
|
|
irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
|
|
|
return 0;
|
|
|
@@ -3303,27 +3441,6 @@ io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
-int io_apic_setup_irq_pin_once(unsigned int irq, int node,
|
|
|
- struct io_apic_irq_attr *attr)
|
|
|
-{
|
|
|
- unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
|
|
|
- int ret;
|
|
|
- struct IO_APIC_route_entry orig_entry;
|
|
|
-
|
|
|
- /* Avoid redundant programming */
|
|
|
- if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
|
|
|
- pr_debug("Pin %d-%d already programmed\n", mpc_ioapic_id(ioapic_idx), pin);
|
|
|
- orig_entry = ioapic_read_entry(attr->ioapic, pin);
|
|
|
- if (attr->trigger == orig_entry.trigger && attr->polarity == orig_entry.polarity)
|
|
|
- return 0;
|
|
|
- return -EBUSY;
|
|
|
- }
|
|
|
- ret = io_apic_setup_irq_pin(irq, node, attr);
|
|
|
- if (!ret)
|
|
|
- set_bit(pin, ioapics[ioapic_idx].pin_programmed);
|
|
|
- return ret;
|
|
|
-}
|
|
|
-
|
|
|
static int __init io_apic_get_redir_entries(int ioapic)
|
|
|
{
|
|
|
union IO_APIC_reg_01 reg_01;
|
|
|
@@ -3340,20 +3457,13 @@ static int __init io_apic_get_redir_entries(int ioapic)
|
|
|
return reg_01.bits.entries + 1;
|
|
|
}
|
|
|
|
|
|
-static void __init probe_nr_irqs_gsi(void)
|
|
|
-{
|
|
|
- int nr;
|
|
|
-
|
|
|
- nr = gsi_top + NR_IRQS_LEGACY;
|
|
|
- if (nr > nr_irqs_gsi)
|
|
|
- nr_irqs_gsi = nr;
|
|
|
-
|
|
|
- printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
|
|
|
-}
|
|
|
-
|
|
|
unsigned int arch_dynirq_lower_bound(unsigned int from)
|
|
|
{
|
|
|
- return from < nr_irqs_gsi ? nr_irqs_gsi : from;
|
|
|
+ /*
|
|
|
+ * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
|
|
|
+ * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
|
|
|
+ */
|
|
|
+ return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
|
|
|
}
|
|
|
|
|
|
int __init arch_probe_nr_irqs(void)
|
|
|
@@ -3363,33 +3473,17 @@ int __init arch_probe_nr_irqs(void)
|
|
|
if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
|
|
|
nr_irqs = NR_VECTORS * nr_cpu_ids;
|
|
|
|
|
|
- nr = nr_irqs_gsi + 8 * nr_cpu_ids;
|
|
|
+ nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
|
|
|
#if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
|
|
|
/*
|
|
|
* for MSI and HT dyn irq
|
|
|
*/
|
|
|
- nr += nr_irqs_gsi * 16;
|
|
|
+ nr += gsi_top * 16;
|
|
|
#endif
|
|
|
if (nr < nr_irqs)
|
|
|
nr_irqs = nr;
|
|
|
|
|
|
- return NR_IRQS_LEGACY;
|
|
|
-}
|
|
|
-
|
|
|
-int io_apic_set_pci_routing(struct device *dev, int irq,
|
|
|
- struct io_apic_irq_attr *irq_attr)
|
|
|
-{
|
|
|
- int node;
|
|
|
-
|
|
|
- if (!IO_APIC_IRQ(irq)) {
|
|
|
- apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
|
|
|
- irq_attr->ioapic);
|
|
|
- return -EINVAL;
|
|
|
- }
|
|
|
-
|
|
|
- node = dev ? dev_to_node(dev) : cpu_to_node(0);
|
|
|
-
|
|
|
- return io_apic_setup_irq_pin_once(irq, node, irq_attr);
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
#ifdef CONFIG_X86_32
|
|
|
@@ -3483,9 +3577,8 @@ static u8 __init io_apic_unique_id(u8 id)
|
|
|
DECLARE_BITMAP(used, 256);
|
|
|
|
|
|
bitmap_zero(used, 256);
|
|
|
- for (i = 0; i < nr_ioapics; i++) {
|
|
|
+ for_each_ioapic(i)
|
|
|
__set_bit(mpc_ioapic_id(i), used);
|
|
|
- }
|
|
|
if (!test_bit(id, used))
|
|
|
return id;
|
|
|
return find_first_zero_bit(used, 256);
|
|
|
@@ -3543,14 +3636,13 @@ void __init setup_ioapic_dest(void)
|
|
|
if (skip_ioapic_setup == 1)
|
|
|
return;
|
|
|
|
|
|
- for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
|
|
|
- for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
|
|
|
+ for_each_ioapic_pin(ioapic, pin) {
|
|
|
irq_entry = find_irq_entry(ioapic, pin, mp_INT);
|
|
|
if (irq_entry == -1)
|
|
|
continue;
|
|
|
- irq = pin_2_irq(irq_entry, ioapic, pin);
|
|
|
|
|
|
- if ((ioapic > 0) && (irq > 16))
|
|
|
+ irq = pin_2_irq(irq_entry, ioapic, pin, 0);
|
|
|
+ if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
|
|
|
continue;
|
|
|
|
|
|
idata = irq_get_irq_data(irq);
|
|
|
@@ -3573,29 +3665,33 @@ void __init setup_ioapic_dest(void)
|
|
|
|
|
|
static struct resource *ioapic_resources;
|
|
|
|
|
|
-static struct resource * __init ioapic_setup_resources(int nr_ioapics)
|
|
|
+static struct resource * __init ioapic_setup_resources(void)
|
|
|
{
|
|
|
unsigned long n;
|
|
|
struct resource *res;
|
|
|
char *mem;
|
|
|
- int i;
|
|
|
+ int i, num = 0;
|
|
|
|
|
|
- if (nr_ioapics <= 0)
|
|
|
+ for_each_ioapic(i)
|
|
|
+ num++;
|
|
|
+ if (num == 0)
|
|
|
return NULL;
|
|
|
|
|
|
n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
|
|
|
- n *= nr_ioapics;
|
|
|
+ n *= num;
|
|
|
|
|
|
mem = alloc_bootmem(n);
|
|
|
res = (void *)mem;
|
|
|
|
|
|
- mem += sizeof(struct resource) * nr_ioapics;
|
|
|
+ mem += sizeof(struct resource) * num;
|
|
|
|
|
|
- for (i = 0; i < nr_ioapics; i++) {
|
|
|
- res[i].name = mem;
|
|
|
- res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
|
|
+ num = 0;
|
|
|
+ for_each_ioapic(i) {
|
|
|
+ res[num].name = mem;
|
|
|
+ res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
|
|
snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
|
|
|
mem += IOAPIC_RESOURCE_NAME_SIZE;
|
|
|
+ num++;
|
|
|
}
|
|
|
|
|
|
ioapic_resources = res;
|
|
|
@@ -3609,8 +3705,8 @@ void __init native_io_apic_init_mappings(void)
|
|
|
struct resource *ioapic_res;
|
|
|
int i;
|
|
|
|
|
|
- ioapic_res = ioapic_setup_resources(nr_ioapics);
|
|
|
- for (i = 0; i < nr_ioapics; i++) {
|
|
|
+ ioapic_res = ioapic_setup_resources();
|
|
|
+ for_each_ioapic(i) {
|
|
|
if (smp_found_config) {
|
|
|
ioapic_phys = mpc_ioapic_addr(i);
|
|
|
#ifdef CONFIG_X86_32
|
|
|
@@ -3641,8 +3737,6 @@ fake_ioapic_page:
|
|
|
ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
|
|
|
ioapic_res++;
|
|
|
}
|
|
|
-
|
|
|
- probe_nr_irqs_gsi();
|
|
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}
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void __init ioapic_insert_resources(void)
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@@ -3657,7 +3751,7 @@ void __init ioapic_insert_resources(void)
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return;
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}
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- for (i = 0; i < nr_ioapics; i++) {
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+ for_each_ioapic(i) {
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insert_resource(&iomem_resource, r);
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r++;
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}
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@@ -3665,16 +3759,15 @@ void __init ioapic_insert_resources(void)
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int mp_find_ioapic(u32 gsi)
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{
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- int i = 0;
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+ int i;
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if (nr_ioapics == 0)
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return -1;
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/* Find the IOAPIC that manages this GSI. */
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- for (i = 0; i < nr_ioapics; i++) {
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+ for_each_ioapic(i) {
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struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
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- if ((gsi >= gsi_cfg->gsi_base)
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- && (gsi <= gsi_cfg->gsi_end))
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+ if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
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return i;
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}
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@@ -3686,7 +3779,7 @@ int mp_find_ioapic_pin(int ioapic, u32 gsi)
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{
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struct mp_ioapic_gsi *gsi_cfg;
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- if (WARN_ON(ioapic == -1))
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+ if (WARN_ON(ioapic < 0))
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return -1;
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gsi_cfg = mp_ioapic_gsi_routing(ioapic);
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@@ -3729,7 +3822,8 @@ static __init int bad_ioapic_register(int idx)
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return 0;
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}
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-void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
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+void __init mp_register_ioapic(int id, u32 address, u32 gsi_base,
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+ struct ioapic_domain_cfg *cfg)
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{
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int idx = 0;
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int entries;
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@@ -3743,6 +3837,8 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
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ioapics[idx].mp_config.type = MP_IOAPIC;
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ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
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ioapics[idx].mp_config.apicaddr = address;
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+ ioapics[idx].irqdomain = NULL;
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+ ioapics[idx].irqdomain_cfg = *cfg;
|
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set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
|
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|
|
|
|
@@ -3779,6 +3875,77 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
|
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|
nr_ioapics++;
|
|
|
}
|
|
|
|
|
|
+int mp_irqdomain_map(struct irq_domain *domain, unsigned int virq,
|
|
|
+ irq_hw_number_t hwirq)
|
|
|
+{
|
|
|
+ int ioapic = (int)(long)domain->host_data;
|
|
|
+ struct mp_pin_info *info = mp_pin_info(ioapic, hwirq);
|
|
|
+ struct io_apic_irq_attr attr;
|
|
|
+
|
|
|
+ /* Get default attribute if not set by caller yet */
|
|
|
+ if (!info->set) {
|
|
|
+ u32 gsi = mp_pin_to_gsi(ioapic, hwirq);
|
|
|
+
|
|
|
+ if (acpi_get_override_irq(gsi, &info->trigger,
|
|
|
+ &info->polarity) < 0) {
|
|
|
+ /*
|
|
|
+ * PCI interrupts are always polarity one level
|
|
|
+ * triggered.
|
|
|
+ */
|
|
|
+ info->trigger = 1;
|
|
|
+ info->polarity = 1;
|
|
|
+ }
|
|
|
+ info->node = NUMA_NO_NODE;
|
|
|
+ info->set = 1;
|
|
|
+ }
|
|
|
+ set_io_apic_irq_attr(&attr, ioapic, hwirq, info->trigger,
|
|
|
+ info->polarity);
|
|
|
+
|
|
|
+ return io_apic_setup_irq_pin(virq, info->node, &attr);
|
|
|
+}
|
|
|
+
|
|
|
+void mp_irqdomain_unmap(struct irq_domain *domain, unsigned int virq)
|
|
|
+{
|
|
|
+ struct irq_data *data = irq_get_irq_data(virq);
|
|
|
+ struct irq_cfg *cfg = irq_cfg(virq);
|
|
|
+ int ioapic = (int)(long)domain->host_data;
|
|
|
+ int pin = (int)data->hwirq;
|
|
|
+
|
|
|
+ ioapic_mask_entry(ioapic, pin);
|
|
|
+ __remove_pin_from_irq(cfg, ioapic, pin);
|
|
|
+ WARN_ON(cfg->irq_2_pin != NULL);
|
|
|
+ arch_teardown_hwirq(virq);
|
|
|
+}
|
|
|
+
|
|
|
+int mp_set_gsi_attr(u32 gsi, int trigger, int polarity, int node)
|
|
|
+{
|
|
|
+ int ret = 0;
|
|
|
+ int ioapic, pin;
|
|
|
+ struct mp_pin_info *info;
|
|
|
+
|
|
|
+ ioapic = mp_find_ioapic(gsi);
|
|
|
+ if (ioapic < 0)
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ pin = mp_find_ioapic_pin(ioapic, gsi);
|
|
|
+ info = mp_pin_info(ioapic, pin);
|
|
|
+ trigger = trigger ? 1 : 0;
|
|
|
+ polarity = polarity ? 1 : 0;
|
|
|
+
|
|
|
+ mutex_lock(&ioapic_mutex);
|
|
|
+ if (!info->set) {
|
|
|
+ info->trigger = trigger;
|
|
|
+ info->polarity = polarity;
|
|
|
+ info->node = node;
|
|
|
+ info->set = 1;
|
|
|
+ } else if (info->trigger != trigger || info->polarity != polarity) {
|
|
|
+ ret = -EBUSY;
|
|
|
+ }
|
|
|
+ mutex_unlock(&ioapic_mutex);
|
|
|
+
|
|
|
+ return ret;
|
|
|
+}
|
|
|
+
|
|
|
/* Enable IOAPIC early just for system timer */
|
|
|
void __init pre_init_apic_IRQ0(void)
|
|
|
{
|
Linus Torvalds