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@@ -42,6 +42,11 @@
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#define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO)
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#define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \
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|ATC_DIF(AT_DMA_MEM_IF))
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+#define ATC_DMA_BUSWIDTHS\
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+ (BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) |\
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+ BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |\
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+ BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |\
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+ BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
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/*
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* Initial number of descriptors to allocate for each channel. This could
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@@ -1531,6 +1536,10 @@ static int __init at_dma_probe(struct platform_device *pdev)
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atdma->dma_common.device_pause = atc_pause;
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atdma->dma_common.device_resume = atc_resume;
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atdma->dma_common.device_terminate_all = atc_terminate_all;
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+ atdma->dma_common.src_addr_widths = ATC_DMA_BUSWIDTHS;
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+ atdma->dma_common.dst_addr_widths = ATC_DMA_BUSWIDTHS;
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+ atdma->dma_common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
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+ atdma->dma_common.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
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}
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dma_writel(atdma, EN, AT_DMA_ENABLE);
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