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+BCM2836 per-CPU interrupt controller
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+
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+The BCM2836 has a per-cpu interrupt controller for the timer, PMU
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+events, and SMP IPIs. One of the CPUs may receive interrupts for the
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+peripheral (GPU) events, which chain to the BCM2835-style interrupt
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+controller.
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+
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+Required properties:
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+
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+- compatible: Should be "brcm,bcm2836-l1-intc"
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+- reg: Specifies base physical address and size of the
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+ registers
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+- interrupt-controller: Identifies the node as an interrupt controller
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+- #interrupt-cells: Specifies the number of cells needed to encode an
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+ interrupt source. The value shall be 1
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+
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+Please refer to interrupts.txt in this directory for details of the common
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+Interrupt Controllers bindings used by client devices.
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+
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+The interrupt sources are as follows:
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+
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+0: CNTPSIRQ
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+1: CNTPNSIRQ
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+2: CNTHPIRQ
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+3: CNTVIRQ
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+8: GPU_FAST
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+9: PMU_FAST
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+
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+Example:
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+
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+local_intc: local_intc {
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+ compatible = "brcm,bcm2836-l1-intc";
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+ reg = <0x40000000 0x100>;
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ interrupt-parent = <&local_intc>;
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+};
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