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@@ -143,6 +143,30 @@ void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
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}
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}
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+/*
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+ * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
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+ * mechanism. This guarantees that we get the real value even if we're
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+ * operating within a Virtual Machine and the Hypervisor is trapping our
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+ * Configuration Space accesses.
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+ */
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+void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
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+{
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+ u32 req = ENABLE | FUNCTION(adap->fn) | reg;
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+
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+ if (is_t4(adap->params.chip))
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+ req |= F_LOCALCFG;
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+
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+ t4_write_reg(adap, PCIE_CFG_SPACE_REQ, req);
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+ *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA);
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+
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+ /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
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+ * Configuration Space read. (None of the other fields matter when
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+ * ENABLE is 0 so a simple register write is easier than a
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+ * read-modify-write via t4_set_reg_field().)
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+ */
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+ t4_write_reg(adap, PCIE_CFG_SPACE_REQ, 0);
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+}
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+
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/*
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* Get the reply to a mailbox command and store it in @rpl in big-endian order.
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*/
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@@ -389,78 +413,41 @@ int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
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return 0;
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}
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-/*
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- * t4_mem_win_rw - read/write memory through PCIE memory window
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- * @adap: the adapter
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- * @addr: address of first byte requested
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- * @data: MEMWIN0_APERTURE bytes of data containing the requested address
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- * @dir: direction of transfer 1 => read, 0 => write
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- *
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- * Read/write MEMWIN0_APERTURE bytes of data from MC starting at a
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- * MEMWIN0_APERTURE-byte-aligned address that covers the requested
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- * address @addr.
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- */
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-static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir)
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-{
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- int i;
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- u32 win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
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-
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- /*
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- * Setup offset into PCIE memory window. Address must be a
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- * MEMWIN0_APERTURE-byte-aligned address. (Read back MA register to
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- * ensure that changes propagate before we attempt to use the new
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- * values.)
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- */
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- t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET,
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- (addr & ~(MEMWIN0_APERTURE - 1)) | win_pf);
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- t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
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-
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- /* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */
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- for (i = 0; i < MEMWIN0_APERTURE; i = i+0x4) {
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- if (dir)
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- *data++ = (__force __be32) t4_read_reg(adap,
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- (MEMWIN0_BASE + i));
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- else
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- t4_write_reg(adap, (MEMWIN0_BASE + i),
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- (__force u32) *data++);
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- }
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-
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- return 0;
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-}
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-
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/**
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* t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
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* @adap: the adapter
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+ * @win: PCI-E Memory Window to use
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* @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
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* @addr: address within indicated memory type
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* @len: amount of memory to transfer
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* @buf: host memory buffer
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- * @dir: direction of transfer 1 => read, 0 => write
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+ * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
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*
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* Reads/writes an [almost] arbitrary memory region in the firmware: the
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- * firmware memory address, length and host buffer must be aligned on
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- * 32-bit boudaries. The memory is transferred as a raw byte sequence
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- * from/to the firmware's memory. If this memory contains data
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- * structures which contain multi-byte integers, it's the callers
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- * responsibility to perform appropriate byte order conversions.
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+ * firmware memory address and host buffer must be aligned on 32-bit
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+ * boudaries; the length may be arbitrary. The memory is transferred as
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+ * a raw byte sequence from/to the firmware's memory. If this memory
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+ * contains data structures which contain multi-byte integers, it's the
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+ * caller's responsibility to perform appropriate byte order conversions.
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*/
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-static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len,
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- __be32 *buf, int dir)
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+int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
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+ u32 len, __be32 *buf, int dir)
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{
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- u32 pos, start, end, offset, memoffset;
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- u32 edc_size, mc_size;
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- int ret = 0;
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- __be32 *data;
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+ u32 pos, offset, resid, memoffset;
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+ u32 edc_size, mc_size, win_pf, mem_reg, mem_aperture, mem_base;
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- /*
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- * Argument sanity checks ...
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+ /* Argument sanity checks ...
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*/
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- if ((addr & 0x3) || (len & 0x3))
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+ if (addr & 0x3)
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return -EINVAL;
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- data = vmalloc(MEMWIN0_APERTURE);
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- if (!data)
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- return -ENOMEM;
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+ /* It's convenient to be able to handle lengths which aren't a
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+ * multiple of 32-bits because we often end up transferring files to
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+ * the firmware. So we'll handle that by normalizing the length here
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+ * and then handling any residual transfer at the end.
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+ */
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+ resid = len & 0x3;
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+ len -= resid;
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/* Offset into the region of memory which is being accessed
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* MEM_EDC0 = 0
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@@ -481,66 +468,98 @@ static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len,
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/* Determine the PCIE_MEM_ACCESS_OFFSET */
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addr = addr + memoffset;
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- /*
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- * The underlaying EDC/MC read routines read MEMWIN0_APERTURE bytes
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- * at a time so we need to round down the start and round up the end.
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- * We'll start copying out of the first line at (addr - start) a word
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- * at a time.
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+ /* Each PCI-E Memory Window is programmed with a window size -- or
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+ * "aperture" -- which controls the granularity of its mapping onto
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+ * adapter memory. We need to grab that aperture in order to know
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+ * how to use the specified window. The window is also programmed
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+ * with the base address of the Memory Window in BAR0's address
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+ * space. For T4 this is an absolute PCI-E Bus Address. For T5
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+ * the address is relative to BAR0.
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*/
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- start = addr & ~(MEMWIN0_APERTURE-1);
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- end = (addr + len + MEMWIN0_APERTURE-1) & ~(MEMWIN0_APERTURE-1);
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- offset = (addr - start)/sizeof(__be32);
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+ mem_reg = t4_read_reg(adap,
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+ PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN,
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+ win));
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+ mem_aperture = 1 << (GET_WINDOW(mem_reg) + 10);
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+ mem_base = GET_PCIEOFST(mem_reg) << 10;
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+ if (is_t4(adap->params.chip))
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+ mem_base -= adap->t4_bar0;
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+ win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
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- for (pos = start; pos < end; pos += MEMWIN0_APERTURE, offset = 0) {
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+ /* Calculate our initial PCI-E Memory Window Position and Offset into
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+ * that Window.
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+ */
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+ pos = addr & ~(mem_aperture-1);
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+ offset = addr - pos;
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- /*
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- * If we're writing, copy the data from the caller's memory
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- * buffer
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+ /* Set up initial PCI-E Memory Window to cover the start of our
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+ * transfer. (Read it back to ensure that changes propagate before we
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+ * attempt to use the new value.)
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+ */
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+ t4_write_reg(adap,
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+ PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win),
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+ pos | win_pf);
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+ t4_read_reg(adap,
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+ PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
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+
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+ /* Transfer data to/from the adapter as long as there's an integral
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+ * number of 32-bit transfers to complete.
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+ */
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+ while (len > 0) {
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+ if (dir == T4_MEMORY_READ)
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+ *buf++ = (__force __be32) t4_read_reg(adap,
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+ mem_base + offset);
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+ else
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+ t4_write_reg(adap, mem_base + offset,
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+ (__force u32) *buf++);
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+ offset += sizeof(__be32);
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+ len -= sizeof(__be32);
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+
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+ /* If we've reached the end of our current window aperture,
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+ * move the PCI-E Memory Window on to the next. Note that
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+ * doing this here after "len" may be 0 allows us to set up
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+ * the PCI-E Memory Window for a possible final residual
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+ * transfer below ...
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*/
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- if (!dir) {
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- /*
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- * If we're doing a partial write, then we need to do
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- * a read-modify-write ...
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- */
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- if (offset || len < MEMWIN0_APERTURE) {
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- ret = t4_mem_win_rw(adap, pos, data, 1);
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- if (ret)
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- break;
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- }
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- while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
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- len > 0) {
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- data[offset++] = *buf++;
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- len -= sizeof(__be32);
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- }
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+ if (offset == mem_aperture) {
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+ pos += mem_aperture;
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+ offset = 0;
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+ t4_write_reg(adap,
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+ PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
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+ win), pos | win_pf);
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+ t4_read_reg(adap,
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+ PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET,
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+ win));
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}
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-
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- /*
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- * Transfer a block of memory and bail if there's an error.
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- */
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- ret = t4_mem_win_rw(adap, pos, data, dir);
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- if (ret)
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- break;
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-
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- /*
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- * If we're reading, copy the data into the caller's memory
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- * buffer.
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- */
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- if (dir)
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- while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
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- len > 0) {
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- *buf++ = data[offset++];
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- len -= sizeof(__be32);
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- }
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}
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- vfree(data);
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- return ret;
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-}
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+ /* If the original transfer had a length which wasn't a multiple of
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+ * 32-bits, now's where we need to finish off the transfer of the
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+ * residual amount. The PCI-E Memory Window has already been moved
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+ * above (if necessary) to cover this final transfer.
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+ */
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+ if (resid) {
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+ union {
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+ __be32 word;
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+ char byte[4];
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+ } last;
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+ unsigned char *bp;
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+ int i;
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+
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+ if (dir == T4_MEMORY_WRITE) {
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+ last.word = (__force __be32) t4_read_reg(adap,
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+ mem_base + offset);
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+ for (bp = (unsigned char *)buf, i = resid; i < 4; i++)
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+ bp[i] = last.byte[i];
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+ } else {
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+ last.word = *buf;
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+ for (i = resid; i < 4; i++)
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+ last.byte[i] = 0;
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+ t4_write_reg(adap, mem_base + offset,
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+ (__force u32) last.word);
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+ }
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+ }
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-int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
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- __be32 *buf)
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-{
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- return t4_memory_rw(adap, mtype, addr, len, buf, 0);
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+ return 0;
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}
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#define EEPROM_STAT_ADDR 0x7bfc
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@@ -2504,39 +2523,6 @@ int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
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return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
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}
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-/**
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- * t4_mem_win_read_len - read memory through PCIE memory window
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- * @adap: the adapter
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- * @addr: address of first byte requested aligned on 32b.
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- * @data: len bytes to hold the data read
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- * @len: amount of data to read from window. Must be <=
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- * MEMWIN0_APERATURE after adjusting for 16B for T4 and
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- * 128B for T5 alignment requirements of the the memory window.
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- *
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- * Read len bytes of data from MC starting at @addr.
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- */
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-int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len)
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-{
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- int i, off;
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- u32 win_pf = is_t4(adap->params.chip) ? 0 : V_PFNUM(adap->fn);
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-
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- /* Align on a 2KB boundary.
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- */
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- off = addr & MEMWIN0_APERTURE;
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- if ((addr & 3) || (len + off) > MEMWIN0_APERTURE)
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- return -EINVAL;
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-
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- t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET,
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- (addr & ~MEMWIN0_APERTURE) | win_pf);
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- t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
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-
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- for (i = 0; i < len; i += 4)
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- *data++ = (__force __be32) t4_read_reg(adap,
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- (MEMWIN0_BASE + off + i));
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-
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- return 0;
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-}
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-
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/**
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* t4_mdio_rd - read a PHY register through MDIO
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* @adap: the adapter
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David S. Miller