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@@ -678,7 +678,7 @@ DTLBMissIMMR:
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mtspr SPRN_MD_TWC, r10
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mfspr r10, SPRN_IMMR /* Get current IMMR */
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rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
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- ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
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+ ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
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_PAGE_PRESENT | _PAGE_NO_CACHE
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mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
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@@ -696,7 +696,7 @@ DTLBMissLinear:
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li r11, MD_PS8MEG | MD_SVALID
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mtspr SPRN_MD_TWC, r11
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rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
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- ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
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+ ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
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_PAGE_PRESENT
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mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
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@@ -715,7 +715,7 @@ ITLBMissLinear:
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li r11, MI_PS8MEG | MI_SVALID | _PAGE_EXEC
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mtspr SPRN_MI_TWC, r11
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rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
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- ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
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+ ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_PRIVILEGED | _PAGE_DIRTY | \
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_PAGE_PRESENT
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mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
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