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@@ -20,53 +20,103 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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+#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/spi/sh_msiof.h>
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#include <linux/spi/spi.h>
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-#include <linux/spi/spi_bitbang.h>
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#include <asm/unaligned.h>
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+
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+struct sh_msiof_chipdata {
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+ u16 tx_fifo_size;
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+ u16 rx_fifo_size;
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+ u16 master_flags;
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+};
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+
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struct sh_msiof_spi_priv {
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- struct spi_bitbang bitbang; /* must be first for spi_bitbang.c */
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void __iomem *mapbase;
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struct clk *clk;
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struct platform_device *pdev;
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+ const struct sh_msiof_chipdata *chipdata;
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struct sh_msiof_spi_info *info;
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struct completion done;
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- unsigned long flags;
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int tx_fifo_size;
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int rx_fifo_size;
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};
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-#define TMDR1 0x00
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-#define TMDR2 0x04
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-#define TMDR3 0x08
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-#define RMDR1 0x10
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-#define RMDR2 0x14
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-#define RMDR3 0x18
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-#define TSCR 0x20
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-#define RSCR 0x22
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-#define CTR 0x28
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-#define FCTR 0x30
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-#define STR 0x40
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-#define IER 0x44
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-#define TDR1 0x48
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-#define TDR2 0x4c
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-#define TFDR 0x50
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-#define RDR1 0x58
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-#define RDR2 0x5c
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-#define RFDR 0x60
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-
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-#define CTR_TSCKE (1 << 15)
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-#define CTR_TFSE (1 << 14)
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-#define CTR_TXE (1 << 9)
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-#define CTR_RXE (1 << 8)
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-
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-#define STR_TEOF (1 << 23)
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-#define STR_REOF (1 << 7)
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+#define TMDR1 0x00 /* Transmit Mode Register 1 */
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+#define TMDR2 0x04 /* Transmit Mode Register 2 */
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+#define TMDR3 0x08 /* Transmit Mode Register 3 */
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+#define RMDR1 0x10 /* Receive Mode Register 1 */
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+#define RMDR2 0x14 /* Receive Mode Register 2 */
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+#define RMDR3 0x18 /* Receive Mode Register 3 */
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+#define TSCR 0x20 /* Transmit Clock Select Register */
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+#define RSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */
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+#define CTR 0x28 /* Control Register */
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+#define FCTR 0x30 /* FIFO Control Register */
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+#define STR 0x40 /* Status Register */
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+#define IER 0x44 /* Interrupt Enable Register */
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+#define TDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */
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+#define TDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */
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+#define TFDR 0x50 /* Transmit FIFO Data Register */
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+#define RDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */
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+#define RDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */
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+#define RFDR 0x60 /* Receive FIFO Data Register */
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+
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+/* TMDR1 and RMDR1 */
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+#define MDR1_TRMD 0x80000000 /* Transfer Mode (1 = Master mode) */
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+#define MDR1_SYNCMD_MASK 0x30000000 /* SYNC Mode */
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+#define MDR1_SYNCMD_SPI 0x20000000 /* Level mode/SPI */
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+#define MDR1_SYNCMD_LR 0x30000000 /* L/R mode */
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+#define MDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
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+#define MDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
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+#define MDR1_FLD_MASK 0x000000c0 /* Frame Sync Signal Interval (0-3) */
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+#define MDR1_FLD_SHIFT 2
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+#define MDR1_XXSTP 0x00000001 /* Transmission/Reception Stop on FIFO */
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+/* TMDR1 */
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+#define TMDR1_PCON 0x40000000 /* Transfer Signal Connection */
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+
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+/* TMDR2 and RMDR2 */
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+#define MDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
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+#define MDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */
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+#define MDR2_GRPMASK1 0x00000001 /* Group Output Mask 1 (SH, A1) */
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+
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+/* TSCR and RSCR */
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+#define SCR_BRPS_MASK 0x1f00 /* Prescaler Setting (1-32) */
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+#define SCR_BRPS(i) (((i) - 1) << 8)
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+#define SCR_BRDV_MASK 0x0007 /* Baud Rate Generator's Division Ratio */
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+#define SCR_BRDV_DIV_2 0x0000
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+#define SCR_BRDV_DIV_4 0x0001
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+#define SCR_BRDV_DIV_8 0x0002
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+#define SCR_BRDV_DIV_16 0x0003
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+#define SCR_BRDV_DIV_32 0x0004
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+#define SCR_BRDV_DIV_1 0x0007
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+
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+/* CTR */
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+#define CTR_TSCKIZ_MASK 0xc0000000 /* Transmit Clock I/O Polarity Select */
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+#define CTR_TSCKIZ_SCK 0x80000000 /* Disable SCK when TX disabled */
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+#define CTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */
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+#define CTR_RSCKIZ_MASK 0x30000000 /* Receive Clock Polarity Select */
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+#define CTR_RSCKIZ_SCK 0x20000000 /* Must match CTR_TSCKIZ_SCK */
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+#define CTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */
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+#define CTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */
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+#define CTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */
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+#define CTR_TXDIZ_MASK 0x00c00000 /* Pin Output When TX is Disabled */
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+#define CTR_TXDIZ_LOW 0x00000000 /* 0 */
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+#define CTR_TXDIZ_HIGH 0x00400000 /* 1 */
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+#define CTR_TXDIZ_HIZ 0x00800000 /* High-impedance */
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+#define CTR_TSCKE 0x00008000 /* Transmit Serial Clock Output Enable */
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+#define CTR_TFSE 0x00004000 /* Transmit Frame Sync Signal Output Enable */
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+#define CTR_TXE 0x00000200 /* Transmit Enable */
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+#define CTR_RXE 0x00000100 /* Receive Enable */
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+
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+/* STR and IER */
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+#define STR_TEOF 0x00800000 /* Frame Transmission End */
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+#define STR_REOF 0x00000080 /* Frame Reception End */
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+
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static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs)
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{
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@@ -130,22 +180,21 @@ static struct {
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unsigned short div;
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unsigned short scr;
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} const sh_msiof_spi_clk_table[] = {
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- { 1, 0x0007 },
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- { 2, 0x0000 },
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- { 4, 0x0001 },
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- { 8, 0x0002 },
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- { 16, 0x0003 },
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- { 32, 0x0004 },
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- { 64, 0x1f00 },
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- { 128, 0x1f01 },
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- { 256, 0x1f02 },
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- { 512, 0x1f03 },
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- { 1024, 0x1f04 },
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+ { 1, SCR_BRPS( 1) | SCR_BRDV_DIV_1 },
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+ { 2, SCR_BRPS( 1) | SCR_BRDV_DIV_2 },
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+ { 4, SCR_BRPS( 1) | SCR_BRDV_DIV_4 },
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+ { 8, SCR_BRPS( 1) | SCR_BRDV_DIV_8 },
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+ { 16, SCR_BRPS( 1) | SCR_BRDV_DIV_16 },
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+ { 32, SCR_BRPS( 1) | SCR_BRDV_DIV_32 },
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+ { 64, SCR_BRPS(32) | SCR_BRDV_DIV_2 },
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+ { 128, SCR_BRPS(32) | SCR_BRDV_DIV_4 },
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+ { 256, SCR_BRPS(32) | SCR_BRDV_DIV_8 },
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+ { 512, SCR_BRPS(32) | SCR_BRDV_DIV_16 },
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+ { 1024, SCR_BRPS(32) | SCR_BRDV_DIV_32 },
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};
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static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
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- unsigned long parent_rate,
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- unsigned long spi_hz)
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+ unsigned long parent_rate, u32 spi_hz)
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{
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unsigned long div = 1024;
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size_t k;
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@@ -163,7 +212,8 @@ static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
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k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
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sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
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- sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
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+ if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))
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+ sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
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}
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static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
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@@ -182,21 +232,25 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
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*/
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sh_msiof_write(p, FCTR, 0);
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- tmp = 0;
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- tmp |= !cs_high << 25;
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- tmp |= lsb_first << 24;
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- sh_msiof_write(p, TMDR1, 0xe0000005 | tmp);
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- sh_msiof_write(p, RMDR1, 0x20000005 | tmp);
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+ tmp = MDR1_SYNCMD_SPI | 1 << MDR1_FLD_SHIFT | MDR1_XXSTP;
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+ tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
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+ tmp |= lsb_first << MDR1_BITLSB_SHIFT;
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+ sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
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+ if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
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+ /* These bits are reserved if RX needs TX */
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+ tmp &= ~0x0000ffff;
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+ }
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+ sh_msiof_write(p, RMDR1, tmp);
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- tmp = 0xa0000000;
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- tmp |= cpol << 30; /* TSCKIZ */
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- tmp |= cpol << 28; /* RSCKIZ */
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+ tmp = 0;
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+ tmp |= CTR_TSCKIZ_SCK | cpol << CTR_TSCKIZ_POL_SHIFT;
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+ tmp |= CTR_RSCKIZ_SCK | cpol << CTR_RSCKIZ_POL_SHIFT;
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edge = cpol ^ !cpha;
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- tmp |= edge << 27; /* TEDG */
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- tmp |= edge << 26; /* REDG */
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- tmp |= (tx_hi_z ? 2 : 0) << 22; /* TXDIZ */
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+ tmp |= edge << CTR_TEDG_SHIFT;
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+ tmp |= edge << CTR_REDG_SHIFT;
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+ tmp |= tx_hi_z ? CTR_TXDIZ_HIZ : CTR_TXDIZ_LOW;
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sh_msiof_write(p, CTR, tmp);
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}
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@@ -204,12 +258,12 @@ static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p,
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const void *tx_buf, void *rx_buf,
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u32 bits, u32 words)
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{
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- u32 dr2 = ((bits - 1) << 24) | ((words - 1) << 16);
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+ u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
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- if (tx_buf)
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+ if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX))
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sh_msiof_write(p, TMDR2, dr2);
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else
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- sh_msiof_write(p, TMDR2, dr2 | 1);
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+ sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
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if (rx_buf)
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sh_msiof_write(p, RMDR2, dr2);
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@@ -362,77 +416,45 @@ static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p,
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put_unaligned(swab32(sh_msiof_read(p, RFDR) >> fs), &buf_32[k]);
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}
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-static int sh_msiof_spi_bits(struct spi_device *spi, struct spi_transfer *t)
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+static int sh_msiof_spi_setup(struct spi_device *spi)
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{
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- int bits;
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-
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- bits = t ? t->bits_per_word : 0;
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- if (!bits)
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- bits = spi->bits_per_word;
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- return bits;
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-}
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-
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-static unsigned long sh_msiof_spi_hz(struct spi_device *spi,
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- struct spi_transfer *t)
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-{
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- unsigned long hz;
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-
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- hz = t ? t->speed_hz : 0;
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- if (!hz)
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- hz = spi->max_speed_hz;
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- return hz;
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-}
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+ struct device_node *np = spi->master->dev.of_node;
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+ struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
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-static int sh_msiof_spi_setup_transfer(struct spi_device *spi,
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- struct spi_transfer *t)
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-{
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- int bits;
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+ if (!np) {
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+ /*
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+ * Use spi->controller_data for CS (same strategy as spi_gpio),
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+ * if any. otherwise let HW control CS
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+ */
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+ spi->cs_gpio = (uintptr_t)spi->controller_data;
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+ }
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- /* noting to check hz values against since parent clock is disabled */
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+ /* Configure pins before deasserting CS */
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+ sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
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+ !!(spi->mode & SPI_CPHA),
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+ !!(spi->mode & SPI_3WIRE),
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+ !!(spi->mode & SPI_LSB_FIRST),
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+ !!(spi->mode & SPI_CS_HIGH));
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- bits = sh_msiof_spi_bits(spi, t);
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- if (bits < 8)
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- return -EINVAL;
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- if (bits > 32)
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- return -EINVAL;
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+ if (spi->cs_gpio >= 0)
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+ gpio_set_value(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH));
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- return spi_bitbang_setup_transfer(spi, t);
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+ return 0;
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}
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-static void sh_msiof_spi_chipselect(struct spi_device *spi, int is_on)
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+static int sh_msiof_prepare_message(struct spi_master *master,
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+ struct spi_message *msg)
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{
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- struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
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- int value;
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-
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- /* chip select is active low unless SPI_CS_HIGH is set */
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- if (spi->mode & SPI_CS_HIGH)
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- value = (is_on == BITBANG_CS_ACTIVE) ? 1 : 0;
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- else
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- value = (is_on == BITBANG_CS_ACTIVE) ? 0 : 1;
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-
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- if (is_on == BITBANG_CS_ACTIVE) {
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- if (!test_and_set_bit(0, &p->flags)) {
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- pm_runtime_get_sync(&p->pdev->dev);
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- clk_enable(p->clk);
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- }
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-
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- /* Configure pins before asserting CS */
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- sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
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- !!(spi->mode & SPI_CPHA),
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- !!(spi->mode & SPI_3WIRE),
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- !!(spi->mode & SPI_LSB_FIRST),
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- !!(spi->mode & SPI_CS_HIGH));
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- }
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+ struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
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+ const struct spi_device *spi = msg->spi;
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- /* use spi->controller data for CS (same strategy as spi_gpio) */
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- gpio_set_value((uintptr_t)spi->controller_data, value);
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-
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- if (is_on == BITBANG_CS_INACTIVE) {
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- if (test_and_clear_bit(0, &p->flags)) {
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- clk_disable(p->clk);
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- pm_runtime_put(&p->pdev->dev);
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- }
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- }
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+ /* Configure pins before asserting CS */
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+ sh_msiof_spi_set_pin_regs(p, !!(spi->mode & SPI_CPOL),
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+ !!(spi->mode & SPI_CPHA),
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+ !!(spi->mode & SPI_3WIRE),
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+ !!(spi->mode & SPI_LSB_FIRST),
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+ !!(spi->mode & SPI_CS_HIGH));
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+ return 0;
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}
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static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
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@@ -486,7 +508,7 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
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/* clear status bits */
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sh_msiof_reset_str(p);
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- /* shut down frame, tx/tx and clock signals */
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+ /* shut down frame, rx/tx and clock signals */
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ret = sh_msiof_modify_ctr_wait(p, CTR_TFSE, 0);
|
|
|
ret = ret ? ret : sh_msiof_modify_ctr_wait(p, CTR_TXE, 0);
|
|
|
if (rx_buf)
|
|
|
@@ -504,9 +526,11 @@ static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p,
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|
return ret;
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|
|
}
|
|
|
|
|
|
-static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
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|
|
+static int sh_msiof_transfer_one(struct spi_master *master,
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|
+ struct spi_device *spi,
|
|
|
+ struct spi_transfer *t)
|
|
|
{
|
|
|
- struct sh_msiof_spi_priv *p = spi_master_get_devdata(spi->master);
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|
|
+ struct sh_msiof_spi_priv *p = spi_master_get_devdata(master);
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|
void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int);
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|
void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int);
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|
int bits;
|
|
|
@@ -516,7 +540,7 @@ static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
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|
|
int n;
|
|
|
bool swab;
|
|
|
|
|
|
- bits = sh_msiof_spi_bits(spi, t);
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|
+ bits = t->bits_per_word;
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|
|
|
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|
if (bits <= 8 && t->len > 15 && !(t->len & 3)) {
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|
bits = 32;
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|
@@ -566,8 +590,7 @@ static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
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|
}
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|
|
|
|
|
/* setup clocks (clock already enabled in chipselect()) */
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|
- sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk),
|
|
|
- sh_msiof_spi_hz(spi, t));
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|
+ sh_msiof_spi_set_clk_regs(p, clk_get_rate(p->clk), t->speed_hz);
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|
|
|
|
|
/* transfer in fifo sized chunks */
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|
words = t->len / bytes_per_word;
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|
@@ -587,22 +610,36 @@ static int sh_msiof_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
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|
words -= n;
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}
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|
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|
- return bytes_done;
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|
|
-}
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|
-
|
|
|
-static u32 sh_msiof_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
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- u32 word, u8 bits)
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-{
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|
- BUG(); /* unused but needed by bitbang code */
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|
return 0;
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|
}
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|
|
+static const struct sh_msiof_chipdata sh_data = {
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+ .tx_fifo_size = 64,
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+ .rx_fifo_size = 64,
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+ .master_flags = 0,
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|
|
+};
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+
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|
|
+static const struct sh_msiof_chipdata r8a779x_data = {
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+ .tx_fifo_size = 64,
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|
+ .rx_fifo_size = 256,
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|
|
+ .master_flags = SPI_MASTER_MUST_TX,
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|
|
+};
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|
|
+
|
|
|
+static const struct of_device_id sh_msiof_match[] = {
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|
+ { .compatible = "renesas,sh-msiof", .data = &sh_data },
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|
|
+ { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
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|
|
+ { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data },
|
|
|
+ { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data },
|
|
|
+ {},
|
|
|
+};
|
|
|
+MODULE_DEVICE_TABLE(of, sh_msiof_match);
|
|
|
+
|
|
|
#ifdef CONFIG_OF
|
|
|
static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev)
|
|
|
{
|
|
|
struct sh_msiof_spi_info *info;
|
|
|
struct device_node *np = dev->of_node;
|
|
|
- u32 num_cs = 0;
|
|
|
+ u32 num_cs = 1;
|
|
|
|
|
|
info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL);
|
|
|
if (!info) {
|
|
|
@@ -632,6 +669,7 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
|
|
|
{
|
|
|
struct resource *r;
|
|
|
struct spi_master *master;
|
|
|
+ const struct of_device_id *of_id;
|
|
|
struct sh_msiof_spi_priv *p;
|
|
|
int i;
|
|
|
int ret;
|
|
|
@@ -645,10 +683,15 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
|
|
|
p = spi_master_get_devdata(master);
|
|
|
|
|
|
platform_set_drvdata(pdev, p);
|
|
|
- if (pdev->dev.of_node)
|
|
|
+
|
|
|
+ of_id = of_match_device(sh_msiof_match, &pdev->dev);
|
|
|
+ if (of_id) {
|
|
|
+ p->chipdata = of_id->data;
|
|
|
p->info = sh_msiof_spi_parse_dt(&pdev->dev);
|
|
|
- else
|
|
|
+ } else {
|
|
|
+ p->chipdata = (const void *)pdev->id_entry->driver_data;
|
|
|
p->info = dev_get_platdata(&pdev->dev);
|
|
|
+ }
|
|
|
|
|
|
if (!p->info) {
|
|
|
dev_err(&pdev->dev, "failed to obtain device info\n");
|
|
|
@@ -686,49 +729,40 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
|
|
|
goto err1;
|
|
|
}
|
|
|
|
|
|
- ret = clk_prepare(p->clk);
|
|
|
- if (ret < 0) {
|
|
|
- dev_err(&pdev->dev, "unable to prepare clock\n");
|
|
|
- goto err1;
|
|
|
- }
|
|
|
-
|
|
|
p->pdev = pdev;
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
|
- /* The standard version of MSIOF use 64 word FIFOs */
|
|
|
- p->tx_fifo_size = 64;
|
|
|
- p->rx_fifo_size = 64;
|
|
|
-
|
|
|
/* Platform data may override FIFO sizes */
|
|
|
+ p->tx_fifo_size = p->chipdata->tx_fifo_size;
|
|
|
+ p->rx_fifo_size = p->chipdata->rx_fifo_size;
|
|
|
if (p->info->tx_fifo_override)
|
|
|
p->tx_fifo_size = p->info->tx_fifo_override;
|
|
|
if (p->info->rx_fifo_override)
|
|
|
p->rx_fifo_size = p->info->rx_fifo_override;
|
|
|
|
|
|
- /* init master and bitbang code */
|
|
|
+ /* init master code */
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
|
|
|
master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
|
|
|
- master->flags = 0;
|
|
|
+ master->flags = p->chipdata->master_flags;
|
|
|
master->bus_num = pdev->id;
|
|
|
+ master->dev.of_node = pdev->dev.of_node;
|
|
|
master->num_chipselect = p->info->num_chipselect;
|
|
|
- master->setup = spi_bitbang_setup;
|
|
|
- master->cleanup = spi_bitbang_cleanup;
|
|
|
-
|
|
|
- p->bitbang.master = master;
|
|
|
- p->bitbang.chipselect = sh_msiof_spi_chipselect;
|
|
|
- p->bitbang.setup_transfer = sh_msiof_spi_setup_transfer;
|
|
|
- p->bitbang.txrx_bufs = sh_msiof_spi_txrx;
|
|
|
- p->bitbang.txrx_word[SPI_MODE_0] = sh_msiof_spi_txrx_word;
|
|
|
- p->bitbang.txrx_word[SPI_MODE_1] = sh_msiof_spi_txrx_word;
|
|
|
- p->bitbang.txrx_word[SPI_MODE_2] = sh_msiof_spi_txrx_word;
|
|
|
- p->bitbang.txrx_word[SPI_MODE_3] = sh_msiof_spi_txrx_word;
|
|
|
-
|
|
|
- ret = spi_bitbang_start(&p->bitbang);
|
|
|
- if (ret == 0)
|
|
|
- return 0;
|
|
|
+ master->setup = sh_msiof_spi_setup;
|
|
|
+ master->prepare_message = sh_msiof_prepare_message;
|
|
|
+ master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32);
|
|
|
+ master->auto_runtime_pm = true;
|
|
|
+ master->transfer_one = sh_msiof_transfer_one;
|
|
|
+
|
|
|
+ ret = devm_spi_register_master(&pdev->dev, master);
|
|
|
+ if (ret < 0) {
|
|
|
+ dev_err(&pdev->dev, "spi_register_master error.\n");
|
|
|
+ goto err2;
|
|
|
+ }
|
|
|
|
|
|
+ return 0;
|
|
|
+
|
|
|
+ err2:
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
- clk_unprepare(p->clk);
|
|
|
err1:
|
|
|
spi_master_put(master);
|
|
|
return ret;
|
|
|
@@ -736,30 +770,22 @@ static int sh_msiof_spi_probe(struct platform_device *pdev)
|
|
|
|
|
|
static int sh_msiof_spi_remove(struct platform_device *pdev)
|
|
|
{
|
|
|
- struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev);
|
|
|
- int ret;
|
|
|
-
|
|
|
- ret = spi_bitbang_stop(&p->bitbang);
|
|
|
- if (!ret) {
|
|
|
- pm_runtime_disable(&pdev->dev);
|
|
|
- clk_unprepare(p->clk);
|
|
|
- spi_master_put(p->bitbang.master);
|
|
|
- }
|
|
|
- return ret;
|
|
|
+ pm_runtime_disable(&pdev->dev);
|
|
|
+ return 0;
|
|
|
}
|
|
|
|
|
|
-#ifdef CONFIG_OF
|
|
|
-static const struct of_device_id sh_msiof_match[] = {
|
|
|
- { .compatible = "renesas,sh-msiof", },
|
|
|
- { .compatible = "renesas,sh-mobile-msiof", },
|
|
|
+static struct platform_device_id spi_driver_ids[] = {
|
|
|
+ { "spi_sh_msiof", (kernel_ulong_t)&sh_data },
|
|
|
+ { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data },
|
|
|
+ { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data },
|
|
|
{},
|
|
|
};
|
|
|
-MODULE_DEVICE_TABLE(of, sh_msiof_match);
|
|
|
-#endif
|
|
|
+MODULE_DEVICE_TABLE(platform, spi_driver_ids);
|
|
|
|
|
|
static struct platform_driver sh_msiof_spi_drv = {
|
|
|
.probe = sh_msiof_spi_probe,
|
|
|
.remove = sh_msiof_spi_remove,
|
|
|
+ .id_table = spi_driver_ids,
|
|
|
.driver = {
|
|
|
.name = "spi_sh_msiof",
|
|
|
.owner = THIS_MODULE,
|
Mark Brown
11 anos atrás