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@@ -4421,6 +4421,18 @@ static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
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ref, mask);
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}
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+static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
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+{
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+ struct amdgpu_device *adev = ring->adev;
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+ uint32_t value = 0;
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+
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+ value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
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+ value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
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+ value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
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+ value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
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+ WREG32(mmSQ_CMD, value);
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+}
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+
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static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
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enum amdgpu_interrupt_state state)
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{
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@@ -4743,6 +4755,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
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.emit_wreg = gfx_v9_0_ring_emit_wreg,
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.emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
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.emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
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+ .soft_recovery = gfx_v9_0_ring_soft_recovery,
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};
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static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
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