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@@ -2522,6 +2522,7 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
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enum pipe pipe = intel_crtc->pipe;
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struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
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uint16_t alloc_size, start, cursor_blocks;
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+ uint16_t minimum[I915_MAX_PLANES];
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unsigned int total_data_rate;
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int plane;
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@@ -2540,9 +2541,21 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
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alloc_size -= cursor_blocks;
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alloc->end -= cursor_blocks;
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+ /* 1. Allocate the mininum required blocks for each active plane */
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+ for_each_plane(pipe, plane) {
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+ const struct intel_plane_wm_parameters *p;
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+
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+ p = ¶ms->plane[plane];
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+ if (!p->enabled)
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+ continue;
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+
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+ minimum[plane] = 8;
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+ alloc_size -= minimum[plane];
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+ }
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+
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/*
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- * Each active plane get a portion of the remaining space, in
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- * proportion to the amount of data they need to fetch from memory.
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+ * 2. Distribute the remaining space in proportion to the amount of
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+ * data each plane needs to fetch from memory.
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*
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* FIXME: we may not allocate every single block here.
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*/
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@@ -2564,8 +2577,9 @@ skl_allocate_pipe_ddb(struct drm_crtc *crtc,
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* promote the expression to 64 bits to avoid overflowing, the
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* result is < available as data_rate / total_data_rate < 1
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*/
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- plane_blocks = div_u64((uint64_t)alloc_size * data_rate,
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- total_data_rate);
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+ plane_blocks = minimum[plane];
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+ plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
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+ total_data_rate);
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ddb->plane[pipe][plane].start = start;
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ddb->plane[pipe][plane].end = start + plane_blocks;
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