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@@ -504,41 +504,6 @@ static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
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return 0;
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}
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-/**
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- * sdma_v2_4_load_microcode - load the sDMA ME ucode
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- *
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- * @adev: amdgpu_device pointer
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- *
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- * Loads the sDMA0/1 ucode.
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- * Returns 0 for success, -EINVAL if the ucode is not available.
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- */
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-static int sdma_v2_4_load_microcode(struct amdgpu_device *adev)
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-{
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- const struct sdma_firmware_header_v1_0 *hdr;
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- const __le32 *fw_data;
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- u32 fw_size;
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- int i, j;
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-
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- /* halt the MEs */
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- sdma_v2_4_enable(adev, false);
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-
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- for (i = 0; i < adev->sdma.num_instances; i++) {
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- if (!adev->sdma.instance[i].fw)
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- return -EINVAL;
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- hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
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- amdgpu_ucode_print_sdma_hdr(&hdr->header);
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- fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
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- fw_data = (const __le32 *)
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- (adev->sdma.instance[i].fw->data +
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- le32_to_cpu(hdr->header.ucode_array_offset_bytes));
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- WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], 0);
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- for (j = 0; j < fw_size; j++)
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- WREG32(mmSDMA0_UCODE_DATA + sdma_offsets[i], le32_to_cpup(fw_data++));
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- WREG32(mmSDMA0_UCODE_ADDR + sdma_offsets[i], adev->sdma.instance[i].fw_version);
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- }
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-
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- return 0;
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-}
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/**
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* sdma_v2_4_start - setup and start the async dma engines
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@@ -552,13 +517,6 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
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{
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int r;
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-
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- if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
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- r = sdma_v2_4_load_microcode(adev);
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- if (r)
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- return r;
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- }
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-
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/* halt the engine before programing */
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sdma_v2_4_enable(adev, false);
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