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+/*
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+ * Copyright (C) 2013 Imagination Technologies
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+ * Author: Paul Burton <paul.burton@imgtec.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms of the GNU General Public License as published by the
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+ * Free Software Foundation; either version 2 of the License, or (at your
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+ * option) any later version.
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+ */
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+#ifndef _ASM_MSA_H
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+#define _ASM_MSA_H
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+
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+#include <asm/mipsregs.h>
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+
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+static inline void enable_msa(void)
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+{
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+ if (cpu_has_msa) {
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+ set_c0_config5(MIPS_CONF5_MSAEN);
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+ enable_fpu_hazard();
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+ }
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+}
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+
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+static inline void disable_msa(void)
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+{
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+ if (cpu_has_msa) {
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+ clear_c0_config5(MIPS_CONF5_MSAEN);
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+ disable_fpu_hazard();
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+ }
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+}
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+
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+static inline int is_msa_enabled(void)
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+{
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+ if (!cpu_has_msa)
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+ return 0;
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+
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+ return read_c0_config5() & MIPS_CONF5_MSAEN;
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+}
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+
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+#ifdef TOOLCHAIN_SUPPORTS_MSA
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+
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+#define __BUILD_MSA_CTL_REG(name, cs) \
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+static inline unsigned int read_msa_##name(void) \
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+{ \
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+ unsigned int reg; \
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+ __asm__ __volatile__( \
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+ " .set push\n" \
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+ " .set msa\n" \
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+ " cfcmsa %0, $" #cs "\n" \
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+ " .set pop\n" \
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+ : "=r"(reg)); \
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+ return reg; \
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+} \
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+ \
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+static inline void write_msa_##name(unsigned int val) \
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+{ \
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+ __asm__ __volatile__( \
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+ " .set push\n" \
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+ " .set msa\n" \
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+ " cfcmsa $" #cs ", %0\n" \
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+ " .set pop\n" \
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+ : : "r"(val)); \
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+}
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+
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+#else /* !TOOLCHAIN_SUPPORTS_MSA */
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+
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+/*
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+ * Define functions using .word for the c[ft]cmsa instructions in order to
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+ * allow compilation with toolchains that do not support MSA. Once all
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+ * toolchains in use support MSA these can be removed.
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+ */
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+
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+#define __BUILD_MSA_CTL_REG(name, cs) \
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+static inline unsigned int read_msa_##name(void) \
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+{ \
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+ unsigned int reg; \
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+ __asm__ __volatile__( \
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+ " .set push\n" \
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+ " .set noat\n" \
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+ " .word 0x787e0059 | (" #cs " << 11)\n" \
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+ " move %0, $1\n" \
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+ " .set pop\n" \
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+ : "=r"(reg)); \
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+ return reg; \
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+} \
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+ \
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+static inline void write_msa_##name(unsigned int val) \
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+{ \
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+ __asm__ __volatile__( \
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+ " .set push\n" \
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+ " .set noat\n" \
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+ " move $1, %0\n" \
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+ " .word 0x783e0819 | (" #cs " << 6)\n" \
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+ " .set pop\n" \
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+ : : "r"(val)); \
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+}
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+
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+#endif /* !TOOLCHAIN_SUPPORTS_MSA */
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+
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+#define MSA_IR 0
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+#define MSA_CSR 1
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+#define MSA_ACCESS 2
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+#define MSA_SAVE 3
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+#define MSA_MODIFY 4
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+#define MSA_REQUEST 5
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+#define MSA_MAP 6
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+#define MSA_UNMAP 7
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+
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+__BUILD_MSA_CTL_REG(ir, 0)
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+__BUILD_MSA_CTL_REG(csr, 1)
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+__BUILD_MSA_CTL_REG(access, 2)
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+__BUILD_MSA_CTL_REG(save, 3)
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+__BUILD_MSA_CTL_REG(modify, 4)
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+__BUILD_MSA_CTL_REG(request, 5)
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+__BUILD_MSA_CTL_REG(map, 6)
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+__BUILD_MSA_CTL_REG(unmap, 7)
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+
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+/* MSA Implementation Register (MSAIR) */
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+#define MSA_IR_REVB 0
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+#define MSA_IR_REVF (_ULCAST_(0xff) << MSA_IR_REVB)
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+#define MSA_IR_PROCB 8
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+#define MSA_IR_PROCF (_ULCAST_(0xff) << MSA_IR_PROCB)
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+#define MSA_IR_WRPB 16
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+#define MSA_IR_WRPF (_ULCAST_(0x1) << MSA_IR_WRPB)
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+
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+/* MSA Control & Status Register (MSACSR) */
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+#define MSA_CSR_RMB 0
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+#define MSA_CSR_RMF (_ULCAST_(0x3) << MSA_CSR_RMB)
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+#define MSA_CSR_RM_NEAREST 0
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+#define MSA_CSR_RM_TO_ZERO 1
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+#define MSA_CSR_RM_TO_POS 2
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+#define MSA_CSR_RM_TO_NEG 3
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+#define MSA_CSR_FLAGSB 2
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+#define MSA_CSR_FLAGSF (_ULCAST_(0x1f) << MSA_CSR_FLAGSB)
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+#define MSA_CSR_FLAGS_IB 2
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+#define MSA_CSR_FLAGS_IF (_ULCAST_(0x1) << MSA_CSR_FLAGS_IB)
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+#define MSA_CSR_FLAGS_UB 3
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+#define MSA_CSR_FLAGS_UF (_ULCAST_(0x1) << MSA_CSR_FLAGS_UB)
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+#define MSA_CSR_FLAGS_OB 4
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+#define MSA_CSR_FLAGS_OF (_ULCAST_(0x1) << MSA_CSR_FLAGS_OB)
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+#define MSA_CSR_FLAGS_ZB 5
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+#define MSA_CSR_FLAGS_ZF (_ULCAST_(0x1) << MSA_CSR_FLAGS_ZB)
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+#define MSA_CSR_FLAGS_VB 6
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+#define MSA_CSR_FLAGS_VF (_ULCAST_(0x1) << MSA_CSR_FLAGS_VB)
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+#define MSA_CSR_ENABLESB 7
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+#define MSA_CSR_ENABLESF (_ULCAST_(0x1f) << MSA_CSR_ENABLESB)
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+#define MSA_CSR_ENABLES_IB 7
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+#define MSA_CSR_ENABLES_IF (_ULCAST_(0x1) << MSA_CSR_ENABLES_IB)
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+#define MSA_CSR_ENABLES_UB 8
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+#define MSA_CSR_ENABLES_UF (_ULCAST_(0x1) << MSA_CSR_ENABLES_UB)
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+#define MSA_CSR_ENABLES_OB 9
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+#define MSA_CSR_ENABLES_OF (_ULCAST_(0x1) << MSA_CSR_ENABLES_OB)
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+#define MSA_CSR_ENABLES_ZB 10
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+#define MSA_CSR_ENABLES_ZF (_ULCAST_(0x1) << MSA_CSR_ENABLES_ZB)
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+#define MSA_CSR_ENABLES_VB 11
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+#define MSA_CSR_ENABLES_VF (_ULCAST_(0x1) << MSA_CSR_ENABLES_VB)
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+#define MSA_CSR_CAUSEB 12
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+#define MSA_CSR_CAUSEF (_ULCAST_(0x3f) << MSA_CSR_CAUSEB)
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+#define MSA_CSR_CAUSE_IB 12
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+#define MSA_CSR_CAUSE_IF (_ULCAST_(0x1) << MSA_CSR_CAUSE_IB)
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+#define MSA_CSR_CAUSE_UB 13
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+#define MSA_CSR_CAUSE_UF (_ULCAST_(0x1) << MSA_CSR_CAUSE_UB)
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+#define MSA_CSR_CAUSE_OB 14
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+#define MSA_CSR_CAUSE_OF (_ULCAST_(0x1) << MSA_CSR_CAUSE_OB)
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+#define MSA_CSR_CAUSE_ZB 15
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+#define MSA_CSR_CAUSE_ZF (_ULCAST_(0x1) << MSA_CSR_CAUSE_ZB)
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+#define MSA_CSR_CAUSE_VB 16
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+#define MSA_CSR_CAUSE_VF (_ULCAST_(0x1) << MSA_CSR_CAUSE_VB)
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+#define MSA_CSR_CAUSE_EB 17
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+#define MSA_CSR_CAUSE_EF (_ULCAST_(0x1) << MSA_CSR_CAUSE_EB)
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+#define MSA_CSR_NXB 18
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+#define MSA_CSR_NXF (_ULCAST_(0x1) << MSA_CSR_NXB)
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+#define MSA_CSR_FSB 24
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+#define MSA_CSR_FSF (_ULCAST_(0x1) << MSA_CSR_FSB)
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+
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+#endif /* _ASM_MSA_H */
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Paul Burton