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@@ -724,6 +724,11 @@ static int vcn_v1_0_start(struct amdgpu_device *adev)
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(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
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(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
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~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
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~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
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+ /* enable system interrupt for JRBC, TODO: move to set interrupt*/
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+ WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
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+ UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
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+ ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
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+
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/* clear the bit 4 of VCN_STATUS */
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/* clear the bit 4 of VCN_STATUS */
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
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WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_STATUS), 0,
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~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
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~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
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@@ -1778,7 +1783,7 @@ static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
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static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
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static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
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{
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{
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- adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 1;
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+ adev->vcn.irq.num_types = adev->vcn.num_enc_rings + 2;
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adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
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adev->vcn.irq.funcs = &vcn_v1_0_irq_funcs;
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}
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}
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