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@@ -47,15 +47,20 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw)
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struct clk_rcg *rcg = to_clk_rcg(hw);
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int num_parents = __clk_get_num_parents(hw->clk);
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u32 ns;
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- int i;
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+ int i, ret;
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- regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
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+ ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
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+ if (ret)
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+ goto err;
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ns = ns_to_src(&rcg->s, ns);
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for (i = 0; i < num_parents; i++)
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if (ns == rcg->s.parent_map[i])
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return i;
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- return -EINVAL;
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+err:
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+ pr_debug("%s: Clock %s has invalid parent, using default.\n",
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+ __func__, __clk_get_name(hw->clk));
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+ return 0;
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}
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static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
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@@ -70,21 +75,28 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
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int num_parents = __clk_get_num_parents(hw->clk);
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u32 ns, reg;
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int bank;
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- int i;
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+ int i, ret;
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struct src_sel *s;
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- regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
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+ ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
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+ if (ret)
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+ goto err;
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bank = reg_to_bank(rcg, reg);
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s = &rcg->s[bank];
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- regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
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+ ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
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+ if (ret)
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+ goto err;
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ns = ns_to_src(s, ns);
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for (i = 0; i < num_parents; i++)
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if (ns == s->parent_map[i])
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return i;
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- return -EINVAL;
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+err:
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+ pr_debug("%s: Clock %s has invalid parent, using default.\n",
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+ __func__, __clk_get_name(hw->clk));
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+ return 0;
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}
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static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
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