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@@ -4,6 +4,8 @@
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#ifndef _ASM_POWERPC_REG_8xx_H
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#define _ASM_POWERPC_REG_8xx_H
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+#include <asm/mmu-8xx.h>
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+
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/* Cache control on the MPC8xx is provided through some additional
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* special purpose registers.
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*/
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@@ -14,6 +16,15 @@
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#define SPRN_DC_ADR 569 /* Address needed for some commands */
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#define SPRN_DC_DAT 570 /* Read-only data register */
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+/* Misc Debug */
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+#define SPRN_DPDR 630
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+#define SPRN_MI_CAM 816
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+#define SPRN_MI_RAM0 817
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+#define SPRN_MI_RAM1 818
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+#define SPRN_MD_CAM 824
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+#define SPRN_MD_RAM0 825
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+#define SPRN_MD_RAM1 826
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+
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/* Commands. Only the first few are available to the instruction cache.
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*/
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#define IDC_ENABLE 0x02000000 /* Cache enable */
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