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@@ -8800,7 +8800,7 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
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struct drm_device *dev = crtc->base.dev;
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intel_clock_t clock, reduced_clock;
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u32 dpll = 0, fp = 0, fp2 = 0;
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- bool ok, has_reduced_clock = false;
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+ bool has_reduced_clock = false;
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bool is_lvds = false;
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struct intel_shared_dpll *pll;
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@@ -8812,14 +8812,15 @@ static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
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WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
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"Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
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- ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
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- &has_reduced_clock, &reduced_clock);
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- if (!ok && !crtc_state->clock_set) {
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- DRM_ERROR("Couldn't find PLL settings for mode!\n");
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- return -EINVAL;
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- }
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- /* Compat-code for transition, will disappear. */
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if (!crtc_state->clock_set) {
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+ if (!ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
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+ &has_reduced_clock,
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+ &reduced_clock)) {
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+ DRM_ERROR("Couldn't find PLL settings for mode!\n");
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+ return -EINVAL;
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+ }
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+
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+ /* Compat-code for transition, will disappear. */
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crtc_state->dpll.n = clock.n;
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crtc_state->dpll.m1 = clock.m1;
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crtc_state->dpll.m2 = clock.m2;
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