|
@@ -64,7 +64,7 @@ void __init check_bugs(void)
|
|
|
* have unknown values. AMD64_LS_CFG MSR is cached in the early AMD
|
|
|
* init code as it is not enumerated and depends on the family.
|
|
|
*/
|
|
|
- if (boot_cpu_has(X86_FEATURE_IBRS))
|
|
|
+ if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
|
|
|
rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
|
|
|
|
|
|
/* Select the proper spectre mitigation before patching alternatives */
|
|
@@ -145,7 +145,7 @@ u64 x86_spec_ctrl_get_default(void)
|
|
|
{
|
|
|
u64 msrval = x86_spec_ctrl_base;
|
|
|
|
|
|
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
|
|
|
+ if (static_cpu_has(X86_FEATURE_SPEC_CTRL))
|
|
|
msrval |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
|
|
|
return msrval;
|
|
|
}
|
|
@@ -155,10 +155,12 @@ void x86_spec_ctrl_set_guest(u64 guest_spec_ctrl)
|
|
|
{
|
|
|
u64 host = x86_spec_ctrl_base;
|
|
|
|
|
|
- if (!boot_cpu_has(X86_FEATURE_IBRS))
|
|
|
+ /* Is MSR_SPEC_CTRL implemented ? */
|
|
|
+ if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
|
|
|
return;
|
|
|
|
|
|
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
|
|
|
+ /* Intel controls SSB in MSR_SPEC_CTRL */
|
|
|
+ if (static_cpu_has(X86_FEATURE_SPEC_CTRL))
|
|
|
host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
|
|
|
|
|
|
if (host != guest_spec_ctrl)
|
|
@@ -170,10 +172,12 @@ void x86_spec_ctrl_restore_host(u64 guest_spec_ctrl)
|
|
|
{
|
|
|
u64 host = x86_spec_ctrl_base;
|
|
|
|
|
|
- if (!boot_cpu_has(X86_FEATURE_IBRS))
|
|
|
+ /* Is MSR_SPEC_CTRL implemented ? */
|
|
|
+ if (!static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
|
|
|
return;
|
|
|
|
|
|
- if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
|
|
|
+ /* Intel controls SSB in MSR_SPEC_CTRL */
|
|
|
+ if (static_cpu_has(X86_FEATURE_SPEC_CTRL))
|
|
|
host |= ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
|
|
|
|
|
|
if (host != guest_spec_ctrl)
|
|
@@ -631,7 +635,7 @@ int arch_prctl_spec_ctrl_get(struct task_struct *task, unsigned long which)
|
|
|
|
|
|
void x86_spec_ctrl_setup_ap(void)
|
|
|
{
|
|
|
- if (boot_cpu_has(X86_FEATURE_IBRS))
|
|
|
+ if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
|
|
|
x86_spec_ctrl_set(x86_spec_ctrl_base & ~x86_spec_ctrl_mask);
|
|
|
|
|
|
if (ssb_mode == SPEC_STORE_BYPASS_DISABLE)
|