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@@ -16,6 +16,11 @@
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* See AMD Publication 43009 "AMD SB700/710/750 Register Reference Guide",
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* AMD Publication 45482 "AMD SB800-Series Southbridges Register
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* Reference Guide"
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+ * AMD Publication 48751 "BIOS and Kernel Developer’s Guide (BKDG)
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+ * for AMD Family 16h Models 00h-0Fh Processors"
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+ * AMD Publication 51192 "AMD Bolton FCH Register Reference Guide"
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+ * AMD Publication 52740 "BIOS and Kernel Developer’s Guide (BKDG)
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+ * for AMD Family 16h Models 30h-3Fh Processors"
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*/
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/*
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@@ -24,38 +29,36 @@
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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+#include <linux/init.h>
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+#include <linux/io.h>
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+#include <linux/ioport.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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-#include <linux/types.h>
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-#include <linux/miscdevice.h>
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-#include <linux/watchdog.h>
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-#include <linux/init.h>
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-#include <linux/fs.h>
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#include <linux/pci.h>
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-#include <linux/ioport.h>
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#include <linux/platform_device.h>
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-#include <linux/uaccess.h>
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-#include <linux/io.h>
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+#include <linux/types.h>
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+#include <linux/watchdog.h>
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#include "sp5100_tco.h"
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-/* Module and version information */
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-#define TCO_VERSION "0.05"
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-#define TCO_MODULE_NAME "SP5100 TCO timer"
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-#define TCO_DRIVER_NAME TCO_MODULE_NAME ", v" TCO_VERSION
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+#define TCO_DRIVER_NAME "sp5100-tco"
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/* internal variables */
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-static u32 tcobase_phys;
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-static u32 tco_wdt_fired;
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-static void __iomem *tcobase;
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-static unsigned int pm_iobase;
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-static DEFINE_SPINLOCK(tco_lock); /* Guards the hardware */
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-static unsigned long timer_alive;
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-static char tco_expect_close;
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-static struct pci_dev *sp5100_tco_pci;
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+
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+enum tco_reg_layout {
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+ sp5100, sb800, efch
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+};
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+
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+struct sp5100_tco {
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+ struct watchdog_device wdd;
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+ void __iomem *tcobase;
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+ enum tco_reg_layout tco_reg_layout;
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+};
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/* the watchdog platform device */
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static struct platform_device *sp5100_tco_platform_device;
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+/* the associated PCI device */
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+static struct pci_dev *sp5100_tco_pci;
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/* module parameters */
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@@ -74,83 +77,105 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started."
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* Some TCO specific functions
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*/
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-static bool tco_has_sp5100_reg_layout(struct pci_dev *dev)
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+static enum tco_reg_layout tco_reg_layout(struct pci_dev *dev)
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{
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- return dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
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- dev->revision < 0x40;
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+ if (dev->vendor == PCI_VENDOR_ID_ATI &&
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+ dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
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+ dev->revision < 0x40) {
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+ return sp5100;
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+ } else if (dev->vendor == PCI_VENDOR_ID_AMD &&
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+ ((dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
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+ dev->revision >= 0x41) ||
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+ (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
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+ dev->revision >= 0x49))) {
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+ return efch;
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+ }
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+ return sb800;
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}
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-static void tco_timer_start(void)
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+static int tco_timer_start(struct watchdog_device *wdd)
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{
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+ struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
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u32 val;
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- unsigned long flags;
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- spin_lock_irqsave(&tco_lock, flags);
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- val = readl(SP5100_WDT_CONTROL(tcobase));
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+ val = readl(SP5100_WDT_CONTROL(tco->tcobase));
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val |= SP5100_WDT_START_STOP_BIT;
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- writel(val, SP5100_WDT_CONTROL(tcobase));
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- spin_unlock_irqrestore(&tco_lock, flags);
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+ writel(val, SP5100_WDT_CONTROL(tco->tcobase));
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+
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+ return 0;
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}
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-static void tco_timer_stop(void)
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+static int tco_timer_stop(struct watchdog_device *wdd)
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{
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+ struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
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u32 val;
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- unsigned long flags;
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- spin_lock_irqsave(&tco_lock, flags);
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- val = readl(SP5100_WDT_CONTROL(tcobase));
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+ val = readl(SP5100_WDT_CONTROL(tco->tcobase));
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val &= ~SP5100_WDT_START_STOP_BIT;
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- writel(val, SP5100_WDT_CONTROL(tcobase));
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- spin_unlock_irqrestore(&tco_lock, flags);
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+ writel(val, SP5100_WDT_CONTROL(tco->tcobase));
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+
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+ return 0;
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}
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-static void tco_timer_keepalive(void)
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+static int tco_timer_ping(struct watchdog_device *wdd)
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{
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+ struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
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u32 val;
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- unsigned long flags;
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- spin_lock_irqsave(&tco_lock, flags);
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- val = readl(SP5100_WDT_CONTROL(tcobase));
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+ val = readl(SP5100_WDT_CONTROL(tco->tcobase));
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val |= SP5100_WDT_TRIGGER_BIT;
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- writel(val, SP5100_WDT_CONTROL(tcobase));
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- spin_unlock_irqrestore(&tco_lock, flags);
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+ writel(val, SP5100_WDT_CONTROL(tco->tcobase));
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+
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+ return 0;
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}
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-static int tco_timer_set_heartbeat(int t)
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+static int tco_timer_set_timeout(struct watchdog_device *wdd,
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+ unsigned int t)
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{
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- unsigned long flags;
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-
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- if (t < 0 || t > 0xffff)
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- return -EINVAL;
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+ struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
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/* Write new heartbeat to watchdog */
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- spin_lock_irqsave(&tco_lock, flags);
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- writel(t, SP5100_WDT_COUNT(tcobase));
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- spin_unlock_irqrestore(&tco_lock, flags);
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+ writel(t, SP5100_WDT_COUNT(tco->tcobase));
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+
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+ wdd->timeout = t;
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- heartbeat = t;
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return 0;
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}
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-static void tco_timer_enable(void)
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+static u8 sp5100_tco_read_pm_reg8(u8 index)
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+{
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+ outb(index, SP5100_IO_PM_INDEX_REG);
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+ return inb(SP5100_IO_PM_DATA_REG);
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+}
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+
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+static void sp5100_tco_update_pm_reg8(u8 index, u8 reset, u8 set)
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+{
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+ u8 val;
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+
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+ outb(index, SP5100_IO_PM_INDEX_REG);
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+ val = inb(SP5100_IO_PM_DATA_REG);
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+ val &= reset;
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+ val |= set;
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+ outb(val, SP5100_IO_PM_DATA_REG);
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+}
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+
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+static void tco_timer_enable(struct sp5100_tco *tco)
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{
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- int val;
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+ u32 val;
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- if (!tco_has_sp5100_reg_layout(sp5100_tco_pci)) {
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+ switch (tco->tco_reg_layout) {
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+ case sb800:
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/* For SB800 or later */
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/* Set the Watchdog timer resolution to 1 sec */
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- outb(SB800_PM_WATCHDOG_CONFIG, SB800_IO_PM_INDEX_REG);
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- val = inb(SB800_IO_PM_DATA_REG);
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- val |= SB800_PM_WATCHDOG_SECOND_RES;
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- outb(val, SB800_IO_PM_DATA_REG);
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+ sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONFIG,
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+ 0xff, SB800_PM_WATCHDOG_SECOND_RES);
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/* Enable watchdog decode bit and watchdog timer */
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- outb(SB800_PM_WATCHDOG_CONTROL, SB800_IO_PM_INDEX_REG);
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- val = inb(SB800_IO_PM_DATA_REG);
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- val |= SB800_PCI_WATCHDOG_DECODE_EN;
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- val &= ~SB800_PM_WATCHDOG_DISABLE;
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- outb(val, SB800_IO_PM_DATA_REG);
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- } else {
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+ sp5100_tco_update_pm_reg8(SB800_PM_WATCHDOG_CONTROL,
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+ ~SB800_PM_WATCHDOG_DISABLE,
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+ SB800_PCI_WATCHDOG_DECODE_EN);
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+ break;
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+ case sp5100:
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/* For SP5100 or SB7x0 */
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/* Enable watchdog decode bit */
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pci_read_config_dword(sp5100_tco_pci,
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@@ -164,409 +189,287 @@ static void tco_timer_enable(void)
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val);
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/* Enable Watchdog timer and set the resolution to 1 sec */
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- outb(SP5100_PM_WATCHDOG_CONTROL, SP5100_IO_PM_INDEX_REG);
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- val = inb(SP5100_IO_PM_DATA_REG);
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- val |= SP5100_PM_WATCHDOG_SECOND_RES;
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- val &= ~SP5100_PM_WATCHDOG_DISABLE;
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- outb(val, SP5100_IO_PM_DATA_REG);
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+ sp5100_tco_update_pm_reg8(SP5100_PM_WATCHDOG_CONTROL,
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+ ~SP5100_PM_WATCHDOG_DISABLE,
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+ SP5100_PM_WATCHDOG_SECOND_RES);
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+ break;
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+ case efch:
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+ /* Set the Watchdog timer resolution to 1 sec and enable */
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+ sp5100_tco_update_pm_reg8(EFCH_PM_DECODEEN3,
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+ ~EFCH_PM_WATCHDOG_DISABLE,
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+ EFCH_PM_DECODEEN_SECOND_RES);
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+ break;
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}
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}
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-/*
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- * /dev/watchdog handling
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- */
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-
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-static int sp5100_tco_open(struct inode *inode, struct file *file)
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+static u32 sp5100_tco_read_pm_reg32(u8 index)
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{
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- /* /dev/watchdog can only be opened once */
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- if (test_and_set_bit(0, &timer_alive))
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- return -EBUSY;
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-
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- /* Reload and activate timer */
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- tco_timer_start();
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- tco_timer_keepalive();
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- return nonseekable_open(inode, file);
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-}
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-
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-static int sp5100_tco_release(struct inode *inode, struct file *file)
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-{
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- /* Shut off the timer. */
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- if (tco_expect_close == 42) {
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- tco_timer_stop();
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- } else {
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- pr_crit("Unexpected close, not stopping watchdog!\n");
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- tco_timer_keepalive();
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- }
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- clear_bit(0, &timer_alive);
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- tco_expect_close = 0;
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- return 0;
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-}
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-
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-static ssize_t sp5100_tco_write(struct file *file, const char __user *data,
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- size_t len, loff_t *ppos)
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-{
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- /* See if we got the magic character 'V' and reload the timer */
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- if (len) {
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- if (!nowayout) {
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- size_t i;
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-
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- /* note: just in case someone wrote the magic character
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- * five months ago... */
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- tco_expect_close = 0;
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+ u32 val = 0;
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+ int i;
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- /* scan to see whether or not we got the magic character
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- */
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- for (i = 0; i != len; i++) {
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- char c;
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- if (get_user(c, data + i))
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- return -EFAULT;
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- if (c == 'V')
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- tco_expect_close = 42;
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- }
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- }
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+ for (i = 3; i >= 0; i--)
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+ val = (val << 8) + sp5100_tco_read_pm_reg8(index + i);
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- /* someone wrote to us, we should reload the timer */
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- tco_timer_keepalive();
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- }
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- return len;
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+ return val;
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}
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-static long sp5100_tco_ioctl(struct file *file, unsigned int cmd,
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- unsigned long arg)
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+static int sp5100_tco_setupdevice(struct device *dev,
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+ struct watchdog_device *wdd)
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{
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- int new_options, retval = -EINVAL;
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- int new_heartbeat;
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- void __user *argp = (void __user *)arg;
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- int __user *p = argp;
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- static const struct watchdog_info ident = {
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- .options = WDIOF_SETTIMEOUT |
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- WDIOF_KEEPALIVEPING |
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- WDIOF_MAGICCLOSE,
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- .firmware_version = 0,
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- .identity = TCO_MODULE_NAME,
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- };
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-
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- switch (cmd) {
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- case WDIOC_GETSUPPORT:
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- return copy_to_user(argp, &ident,
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- sizeof(ident)) ? -EFAULT : 0;
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- case WDIOC_GETSTATUS:
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- case WDIOC_GETBOOTSTATUS:
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- return put_user(0, p);
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- case WDIOC_SETOPTIONS:
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- if (get_user(new_options, p))
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- return -EFAULT;
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- if (new_options & WDIOS_DISABLECARD) {
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- tco_timer_stop();
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- retval = 0;
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- }
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- if (new_options & WDIOS_ENABLECARD) {
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- tco_timer_start();
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- tco_timer_keepalive();
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- retval = 0;
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- }
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- return retval;
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- case WDIOC_KEEPALIVE:
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- tco_timer_keepalive();
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- return 0;
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- case WDIOC_SETTIMEOUT:
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- if (get_user(new_heartbeat, p))
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- return -EFAULT;
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- if (tco_timer_set_heartbeat(new_heartbeat))
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- return -EINVAL;
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- tco_timer_keepalive();
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- /* Fall through */
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- case WDIOC_GETTIMEOUT:
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- return put_user(heartbeat, p);
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- default:
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- return -ENOTTY;
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- }
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-}
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-
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-/*
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- * Kernel Interfaces
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- */
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-
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-static const struct file_operations sp5100_tco_fops = {
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- .owner = THIS_MODULE,
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- .llseek = no_llseek,
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- .write = sp5100_tco_write,
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- .unlocked_ioctl = sp5100_tco_ioctl,
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- .open = sp5100_tco_open,
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- .release = sp5100_tco_release,
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-};
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-
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-static struct miscdevice sp5100_tco_miscdev = {
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- .minor = WATCHDOG_MINOR,
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- .name = "watchdog",
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- .fops = &sp5100_tco_fops,
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-};
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-
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-/*
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- * Data for PCI driver interface
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- *
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- * This data only exists for exporting the supported
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- * PCI ids via MODULE_DEVICE_TABLE. We do not actually
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- * register a pci_driver, because someone else might
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- * want to register another driver on the same PCI id.
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- */
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-static const struct pci_device_id sp5100_tco_pci_tbl[] = {
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- { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
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- PCI_ANY_ID, },
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- { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
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- PCI_ANY_ID, },
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|
|
- { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
|
|
|
- PCI_ANY_ID, },
|
|
|
- { 0, }, /* End of list */
|
|
|
-};
|
|
|
-MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
|
|
|
-
|
|
|
-/*
|
|
|
- * Init & exit routines
|
|
|
- */
|
|
|
-static unsigned char sp5100_tco_setupdevice(void)
|
|
|
-{
|
|
|
- struct pci_dev *dev = NULL;
|
|
|
- const char *dev_name = NULL;
|
|
|
- u32 val;
|
|
|
- u32 index_reg, data_reg, base_addr;
|
|
|
+ struct sp5100_tco *tco = watchdog_get_drvdata(wdd);
|
|
|
+ const char *dev_name;
|
|
|
+ u32 mmio_addr = 0, val;
|
|
|
+ int ret;
|
|
|
|
|
|
- /* Match the PCI device */
|
|
|
- for_each_pci_dev(dev) {
|
|
|
- if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
|
|
|
- sp5100_tco_pci = dev;
|
|
|
- break;
|
|
|
- }
|
|
|
+ /* Request the IO ports used by this driver */
|
|
|
+ if (!request_muxed_region(SP5100_IO_PM_INDEX_REG,
|
|
|
+ SP5100_PM_IOPORTS_SIZE, "sp5100_tco")) {
|
|
|
+ dev_err(dev, "I/O address 0x%04x already in use\n",
|
|
|
+ SP5100_IO_PM_INDEX_REG);
|
|
|
+ return -EBUSY;
|
|
|
}
|
|
|
|
|
|
- if (!sp5100_tco_pci)
|
|
|
- return 0;
|
|
|
-
|
|
|
- pr_info("PCI Vendor ID: 0x%x, Device ID: 0x%x, Revision ID: 0x%x\n",
|
|
|
- sp5100_tco_pci->vendor, sp5100_tco_pci->device,
|
|
|
- sp5100_tco_pci->revision);
|
|
|
-
|
|
|
/*
|
|
|
* Determine type of southbridge chipset.
|
|
|
*/
|
|
|
- if (tco_has_sp5100_reg_layout(sp5100_tco_pci)) {
|
|
|
+ switch (tco->tco_reg_layout) {
|
|
|
+ case sp5100:
|
|
|
dev_name = SP5100_DEVNAME;
|
|
|
- index_reg = SP5100_IO_PM_INDEX_REG;
|
|
|
- data_reg = SP5100_IO_PM_DATA_REG;
|
|
|
- base_addr = SP5100_PM_WATCHDOG_BASE;
|
|
|
- } else {
|
|
|
+ mmio_addr = sp5100_tco_read_pm_reg32(SP5100_PM_WATCHDOG_BASE) &
|
|
|
+ 0xfffffff8;
|
|
|
+ break;
|
|
|
+ case sb800:
|
|
|
dev_name = SB800_DEVNAME;
|
|
|
- index_reg = SB800_IO_PM_INDEX_REG;
|
|
|
- data_reg = SB800_IO_PM_DATA_REG;
|
|
|
- base_addr = SB800_PM_WATCHDOG_BASE;
|
|
|
- }
|
|
|
-
|
|
|
- /* Request the IO ports used by this driver */
|
|
|
- pm_iobase = SP5100_IO_PM_INDEX_REG;
|
|
|
- if (!request_region(pm_iobase, SP5100_PM_IOPORTS_SIZE, dev_name)) {
|
|
|
- pr_err("I/O address 0x%04x already in use\n", pm_iobase);
|
|
|
- goto exit;
|
|
|
+ mmio_addr = sp5100_tco_read_pm_reg32(SB800_PM_WATCHDOG_BASE) &
|
|
|
+ 0xfffffff8;
|
|
|
+ break;
|
|
|
+ case efch:
|
|
|
+ dev_name = SB800_DEVNAME;
|
|
|
+ val = sp5100_tco_read_pm_reg8(EFCH_PM_DECODEEN);
|
|
|
+ if (val & EFCH_PM_DECODEEN_WDT_TMREN)
|
|
|
+ mmio_addr = EFCH_PM_WDT_ADDR;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ return -ENODEV;
|
|
|
}
|
|
|
|
|
|
- /*
|
|
|
- * First, Find the watchdog timer MMIO address from indirect I/O.
|
|
|
- */
|
|
|
- outb(base_addr+3, index_reg);
|
|
|
- val = inb(data_reg);
|
|
|
- outb(base_addr+2, index_reg);
|
|
|
- val = val << 8 | inb(data_reg);
|
|
|
- outb(base_addr+1, index_reg);
|
|
|
- val = val << 8 | inb(data_reg);
|
|
|
- outb(base_addr+0, index_reg);
|
|
|
- /* Low three bits of BASE are reserved */
|
|
|
- val = val << 8 | (inb(data_reg) & 0xf8);
|
|
|
-
|
|
|
- pr_debug("Got 0x%04x from indirect I/O\n", val);
|
|
|
-
|
|
|
/* Check MMIO address conflict */
|
|
|
- if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
|
|
|
- dev_name))
|
|
|
- goto setup_wdt;
|
|
|
- else
|
|
|
- pr_debug("MMIO address 0x%04x already in use\n", val);
|
|
|
-
|
|
|
- /*
|
|
|
- * Secondly, Find the watchdog timer MMIO address
|
|
|
- * from SBResource_MMIO register.
|
|
|
- */
|
|
|
- if (tco_has_sp5100_reg_layout(sp5100_tco_pci)) {
|
|
|
- /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
|
|
|
- pci_read_config_dword(sp5100_tco_pci,
|
|
|
- SP5100_SB_RESOURCE_MMIO_BASE, &val);
|
|
|
- } else {
|
|
|
- /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
|
|
|
- outb(SB800_PM_ACPI_MMIO_EN+3, SB800_IO_PM_INDEX_REG);
|
|
|
- val = inb(SB800_IO_PM_DATA_REG);
|
|
|
- outb(SB800_PM_ACPI_MMIO_EN+2, SB800_IO_PM_INDEX_REG);
|
|
|
- val = val << 8 | inb(SB800_IO_PM_DATA_REG);
|
|
|
- outb(SB800_PM_ACPI_MMIO_EN+1, SB800_IO_PM_INDEX_REG);
|
|
|
- val = val << 8 | inb(SB800_IO_PM_DATA_REG);
|
|
|
- outb(SB800_PM_ACPI_MMIO_EN+0, SB800_IO_PM_INDEX_REG);
|
|
|
- val = val << 8 | inb(SB800_IO_PM_DATA_REG);
|
|
|
+ if (!mmio_addr ||
|
|
|
+ !devm_request_mem_region(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE,
|
|
|
+ dev_name)) {
|
|
|
+ if (mmio_addr)
|
|
|
+ dev_dbg(dev, "MMIO address 0x%08x already in use\n",
|
|
|
+ mmio_addr);
|
|
|
+ switch (tco->tco_reg_layout) {
|
|
|
+ case sp5100:
|
|
|
+ /*
|
|
|
+ * Secondly, Find the watchdog timer MMIO address
|
|
|
+ * from SBResource_MMIO register.
|
|
|
+ */
|
|
|
+ /* Read SBResource_MMIO from PCI config(PCI_Reg: 9Ch) */
|
|
|
+ pci_read_config_dword(sp5100_tco_pci,
|
|
|
+ SP5100_SB_RESOURCE_MMIO_BASE,
|
|
|
+ &mmio_addr);
|
|
|
+ if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
|
|
|
+ SB800_ACPI_MMIO_SEL)) !=
|
|
|
+ SB800_ACPI_MMIO_DECODE_EN) {
|
|
|
+ ret = -ENODEV;
|
|
|
+ goto unreg_region;
|
|
|
+ }
|
|
|
+ mmio_addr &= ~0xFFF;
|
|
|
+ mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
|
|
|
+ break;
|
|
|
+ case sb800:
|
|
|
+ /* Read SBResource_MMIO from AcpiMmioEn(PM_Reg: 24h) */
|
|
|
+ mmio_addr =
|
|
|
+ sp5100_tco_read_pm_reg32(SB800_PM_ACPI_MMIO_EN);
|
|
|
+ if ((mmio_addr & (SB800_ACPI_MMIO_DECODE_EN |
|
|
|
+ SB800_ACPI_MMIO_SEL)) !=
|
|
|
+ SB800_ACPI_MMIO_DECODE_EN) {
|
|
|
+ ret = -ENODEV;
|
|
|
+ goto unreg_region;
|
|
|
+ }
|
|
|
+ mmio_addr &= ~0xFFF;
|
|
|
+ mmio_addr += SB800_PM_WDT_MMIO_OFFSET;
|
|
|
+ break;
|
|
|
+ case efch:
|
|
|
+ val = sp5100_tco_read_pm_reg8(EFCH_PM_ISACONTROL);
|
|
|
+ if (!(val & EFCH_PM_ISACONTROL_MMIOEN)) {
|
|
|
+ ret = -ENODEV;
|
|
|
+ goto unreg_region;
|
|
|
+ }
|
|
|
+ mmio_addr = EFCH_PM_ACPI_MMIO_ADDR +
|
|
|
+ EFCH_PM_ACPI_MMIO_WDT_OFFSET;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ dev_dbg(dev, "Got 0x%08x from SBResource_MMIO register\n",
|
|
|
+ mmio_addr);
|
|
|
+ if (!devm_request_mem_region(dev, mmio_addr,
|
|
|
+ SP5100_WDT_MEM_MAP_SIZE,
|
|
|
+ dev_name)) {
|
|
|
+ dev_dbg(dev, "MMIO address 0x%08x already in use\n",
|
|
|
+ mmio_addr);
|
|
|
+ ret = -EBUSY;
|
|
|
+ goto unreg_region;
|
|
|
+ }
|
|
|
}
|
|
|
|
|
|
- /* The SBResource_MMIO is enabled and mapped memory space? */
|
|
|
- if ((val & (SB800_ACPI_MMIO_DECODE_EN | SB800_ACPI_MMIO_SEL)) ==
|
|
|
- SB800_ACPI_MMIO_DECODE_EN) {
|
|
|
- /* Clear unnecessary the low twelve bits */
|
|
|
- val &= ~0xFFF;
|
|
|
- /* Add the Watchdog Timer offset to base address. */
|
|
|
- val += SB800_PM_WDT_MMIO_OFFSET;
|
|
|
- /* Check MMIO address conflict */
|
|
|
- if (request_mem_region_exclusive(val, SP5100_WDT_MEM_MAP_SIZE,
|
|
|
- dev_name)) {
|
|
|
- pr_debug("Got 0x%04x from SBResource_MMIO register\n",
|
|
|
- val);
|
|
|
- goto setup_wdt;
|
|
|
- } else
|
|
|
- pr_debug("MMIO address 0x%04x already in use\n", val);
|
|
|
- } else
|
|
|
- pr_debug("SBResource_MMIO is disabled(0x%04x)\n", val);
|
|
|
-
|
|
|
- pr_notice("failed to find MMIO address, giving up.\n");
|
|
|
- goto unreg_region;
|
|
|
-
|
|
|
-setup_wdt:
|
|
|
- tcobase_phys = val;
|
|
|
-
|
|
|
- tcobase = ioremap(val, SP5100_WDT_MEM_MAP_SIZE);
|
|
|
- if (!tcobase) {
|
|
|
- pr_err("failed to get tcobase address\n");
|
|
|
- goto unreg_mem_region;
|
|
|
+ tco->tcobase = devm_ioremap(dev, mmio_addr, SP5100_WDT_MEM_MAP_SIZE);
|
|
|
+ if (!tco->tcobase) {
|
|
|
+ dev_err(dev, "failed to get tcobase address\n");
|
|
|
+ ret = -ENOMEM;
|
|
|
+ goto unreg_region;
|
|
|
}
|
|
|
|
|
|
- pr_info("Using 0x%04x for watchdog MMIO address\n", val);
|
|
|
+ dev_info(dev, "Using 0x%08x for watchdog MMIO address\n", mmio_addr);
|
|
|
|
|
|
/* Setup the watchdog timer */
|
|
|
- tco_timer_enable();
|
|
|
+ tco_timer_enable(tco);
|
|
|
+
|
|
|
+ val = readl(SP5100_WDT_CONTROL(tco->tcobase));
|
|
|
+ if (val & SP5100_WDT_DISABLED) {
|
|
|
+ dev_err(dev, "Watchdog hardware is disabled\n");
|
|
|
+ ret = -ENODEV;
|
|
|
+ goto unreg_region;
|
|
|
+ }
|
|
|
|
|
|
- /* Check that the watchdog action is set to reset the system */
|
|
|
- val = readl(SP5100_WDT_CONTROL(tcobase));
|
|
|
/*
|
|
|
* Save WatchDogFired status, because WatchDogFired flag is
|
|
|
* cleared here.
|
|
|
*/
|
|
|
- tco_wdt_fired = val & SP5100_PM_WATCHDOG_FIRED;
|
|
|
- val &= ~SP5100_PM_WATCHDOG_ACTION_RESET;
|
|
|
- writel(val, SP5100_WDT_CONTROL(tcobase));
|
|
|
+ if (val & SP5100_WDT_FIRED)
|
|
|
+ wdd->bootstatus = WDIOF_CARDRESET;
|
|
|
+ /* Set watchdog action to reset the system */
|
|
|
+ val &= ~SP5100_WDT_ACTION_RESET;
|
|
|
+ writel(val, SP5100_WDT_CONTROL(tco->tcobase));
|
|
|
|
|
|
/* Set a reasonable heartbeat before we stop the timer */
|
|
|
- tco_timer_set_heartbeat(heartbeat);
|
|
|
+ tco_timer_set_timeout(wdd, wdd->timeout);
|
|
|
|
|
|
/*
|
|
|
* Stop the TCO before we change anything so we don't race with
|
|
|
* a zeroed timer.
|
|
|
*/
|
|
|
- tco_timer_stop();
|
|
|
+ tco_timer_stop(wdd);
|
|
|
|
|
|
- /* Done */
|
|
|
- return 1;
|
|
|
+ release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
|
|
|
|
|
|
-unreg_mem_region:
|
|
|
- release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
|
|
|
-unreg_region:
|
|
|
- release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
|
|
|
-exit:
|
|
|
return 0;
|
|
|
-}
|
|
|
|
|
|
-static int sp5100_tco_init(struct platform_device *dev)
|
|
|
-{
|
|
|
- int ret;
|
|
|
+unreg_region:
|
|
|
+ release_region(SP5100_IO_PM_INDEX_REG, SP5100_PM_IOPORTS_SIZE);
|
|
|
+ return ret;
|
|
|
+}
|
|
|
|
|
|
- /*
|
|
|
- * Check whether or not the hardware watchdog is there. If found, then
|
|
|
- * set it up.
|
|
|
- */
|
|
|
- if (!sp5100_tco_setupdevice())
|
|
|
- return -ENODEV;
|
|
|
+static struct watchdog_info sp5100_tco_wdt_info = {
|
|
|
+ .identity = "SP5100 TCO timer",
|
|
|
+ .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
|
|
|
+};
|
|
|
|
|
|
- /* Check to see if last reboot was due to watchdog timeout */
|
|
|
- pr_info("Last reboot was %striggered by watchdog.\n",
|
|
|
- tco_wdt_fired ? "" : "not ");
|
|
|
+static const struct watchdog_ops sp5100_tco_wdt_ops = {
|
|
|
+ .owner = THIS_MODULE,
|
|
|
+ .start = tco_timer_start,
|
|
|
+ .stop = tco_timer_stop,
|
|
|
+ .ping = tco_timer_ping,
|
|
|
+ .set_timeout = tco_timer_set_timeout,
|
|
|
+};
|
|
|
|
|
|
- /*
|
|
|
- * Check that the heartbeat value is within it's range.
|
|
|
- * If not, reset to the default.
|
|
|
- */
|
|
|
- if (tco_timer_set_heartbeat(heartbeat)) {
|
|
|
- heartbeat = WATCHDOG_HEARTBEAT;
|
|
|
- tco_timer_set_heartbeat(heartbeat);
|
|
|
- }
|
|
|
+static int sp5100_tco_probe(struct platform_device *pdev)
|
|
|
+{
|
|
|
+ struct device *dev = &pdev->dev;
|
|
|
+ struct watchdog_device *wdd;
|
|
|
+ struct sp5100_tco *tco;
|
|
|
+ int ret;
|
|
|
|
|
|
- ret = misc_register(&sp5100_tco_miscdev);
|
|
|
- if (ret != 0) {
|
|
|
- pr_err("cannot register miscdev on minor=%d (err=%d)\n",
|
|
|
- WATCHDOG_MINOR, ret);
|
|
|
- goto exit;
|
|
|
+ tco = devm_kzalloc(dev, sizeof(*tco), GFP_KERNEL);
|
|
|
+ if (!tco)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ tco->tco_reg_layout = tco_reg_layout(sp5100_tco_pci);
|
|
|
+
|
|
|
+ wdd = &tco->wdd;
|
|
|
+ wdd->parent = dev;
|
|
|
+ wdd->info = &sp5100_tco_wdt_info;
|
|
|
+ wdd->ops = &sp5100_tco_wdt_ops;
|
|
|
+ wdd->timeout = WATCHDOG_HEARTBEAT;
|
|
|
+ wdd->min_timeout = 1;
|
|
|
+ wdd->max_timeout = 0xffff;
|
|
|
+
|
|
|
+ if (watchdog_init_timeout(wdd, heartbeat, NULL))
|
|
|
+ dev_info(dev, "timeout value invalid, using %d\n",
|
|
|
+ wdd->timeout);
|
|
|
+ watchdog_set_nowayout(wdd, nowayout);
|
|
|
+ watchdog_stop_on_reboot(wdd);
|
|
|
+ watchdog_stop_on_unregister(wdd);
|
|
|
+ watchdog_set_drvdata(wdd, tco);
|
|
|
+
|
|
|
+ ret = sp5100_tco_setupdevice(dev, wdd);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ ret = devm_watchdog_register_device(dev, wdd);
|
|
|
+ if (ret) {
|
|
|
+ dev_err(dev, "cannot register watchdog device (err=%d)\n", ret);
|
|
|
+ return ret;
|
|
|
}
|
|
|
|
|
|
- clear_bit(0, &timer_alive);
|
|
|
-
|
|
|
/* Show module parameters */
|
|
|
- pr_info("initialized (0x%p). heartbeat=%d sec (nowayout=%d)\n",
|
|
|
- tcobase, heartbeat, nowayout);
|
|
|
-
|
|
|
- return 0;
|
|
|
-
|
|
|
-exit:
|
|
|
- iounmap(tcobase);
|
|
|
- release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
|
|
|
- release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
|
|
|
- return ret;
|
|
|
-}
|
|
|
-
|
|
|
-static void sp5100_tco_cleanup(void)
|
|
|
-{
|
|
|
- /* Stop the timer before we leave */
|
|
|
- if (!nowayout)
|
|
|
- tco_timer_stop();
|
|
|
-
|
|
|
- /* Deregister */
|
|
|
- misc_deregister(&sp5100_tco_miscdev);
|
|
|
- iounmap(tcobase);
|
|
|
- release_mem_region(tcobase_phys, SP5100_WDT_MEM_MAP_SIZE);
|
|
|
- release_region(pm_iobase, SP5100_PM_IOPORTS_SIZE);
|
|
|
-}
|
|
|
+ dev_info(dev, "initialized. heartbeat=%d sec (nowayout=%d)\n",
|
|
|
+ wdd->timeout, nowayout);
|
|
|
|
|
|
-static int sp5100_tco_remove(struct platform_device *dev)
|
|
|
-{
|
|
|
- if (tcobase)
|
|
|
- sp5100_tco_cleanup();
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
-static void sp5100_tco_shutdown(struct platform_device *dev)
|
|
|
-{
|
|
|
- tco_timer_stop();
|
|
|
-}
|
|
|
-
|
|
|
static struct platform_driver sp5100_tco_driver = {
|
|
|
- .probe = sp5100_tco_init,
|
|
|
- .remove = sp5100_tco_remove,
|
|
|
- .shutdown = sp5100_tco_shutdown,
|
|
|
+ .probe = sp5100_tco_probe,
|
|
|
.driver = {
|
|
|
- .name = TCO_MODULE_NAME,
|
|
|
+ .name = TCO_DRIVER_NAME,
|
|
|
},
|
|
|
};
|
|
|
|
|
|
-static int __init sp5100_tco_init_module(void)
|
|
|
+/*
|
|
|
+ * Data for PCI driver interface
|
|
|
+ *
|
|
|
+ * This data only exists for exporting the supported
|
|
|
+ * PCI ids via MODULE_DEVICE_TABLE. We do not actually
|
|
|
+ * register a pci_driver, because someone else might
|
|
|
+ * want to register another driver on the same PCI id.
|
|
|
+ */
|
|
|
+static const struct pci_device_id sp5100_tco_pci_tbl[] = {
|
|
|
+ { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, PCI_ANY_ID,
|
|
|
+ PCI_ANY_ID, },
|
|
|
+ { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, PCI_ANY_ID,
|
|
|
+ PCI_ANY_ID, },
|
|
|
+ { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, PCI_ANY_ID,
|
|
|
+ PCI_ANY_ID, },
|
|
|
+ { 0, }, /* End of list */
|
|
|
+};
|
|
|
+MODULE_DEVICE_TABLE(pci, sp5100_tco_pci_tbl);
|
|
|
+
|
|
|
+static int __init sp5100_tco_init(void)
|
|
|
{
|
|
|
+ struct pci_dev *dev = NULL;
|
|
|
int err;
|
|
|
|
|
|
- pr_info("SP5100/SB800 TCO WatchDog Timer Driver v%s\n", TCO_VERSION);
|
|
|
+ /* Match the PCI device */
|
|
|
+ for_each_pci_dev(dev) {
|
|
|
+ if (pci_match_id(sp5100_tco_pci_tbl, dev) != NULL) {
|
|
|
+ sp5100_tco_pci = dev;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!sp5100_tco_pci)
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ pr_info("SP5100/SB800 TCO WatchDog Timer Driver\n");
|
|
|
|
|
|
err = platform_driver_register(&sp5100_tco_driver);
|
|
|
if (err)
|
|
|
return err;
|
|
|
|
|
|
- sp5100_tco_platform_device = platform_device_register_simple(
|
|
|
- TCO_MODULE_NAME, -1, NULL, 0);
|
|
|
+ sp5100_tco_platform_device =
|
|
|
+ platform_device_register_simple(TCO_DRIVER_NAME, -1, NULL, 0);
|
|
|
if (IS_ERR(sp5100_tco_platform_device)) {
|
|
|
err = PTR_ERR(sp5100_tco_platform_device);
|
|
|
goto unreg_platform_driver;
|
|
@@ -579,15 +482,14 @@ unreg_platform_driver:
|
|
|
return err;
|
|
|
}
|
|
|
|
|
|
-static void __exit sp5100_tco_cleanup_module(void)
|
|
|
+static void __exit sp5100_tco_exit(void)
|
|
|
{
|
|
|
platform_device_unregister(sp5100_tco_platform_device);
|
|
|
platform_driver_unregister(&sp5100_tco_driver);
|
|
|
- pr_info("SP5100/SB800 TCO Watchdog Module Unloaded\n");
|
|
|
}
|
|
|
|
|
|
-module_init(sp5100_tco_init_module);
|
|
|
-module_exit(sp5100_tco_cleanup_module);
|
|
|
+module_init(sp5100_tco_init);
|
|
|
+module_exit(sp5100_tco_exit);
|
|
|
|
|
|
MODULE_AUTHOR("Priyanka Gupta");
|
|
|
MODULE_DESCRIPTION("TCO timer driver for SP5100/SB800 chipset");
|