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@@ -471,6 +471,9 @@ void mmhub_v1_0_update_power_gating(struct amdgpu_device *adev,
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RENG_EXECUTE_ON_REG_UPDATE, 1);
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RENG_EXECUTE_ON_REG_UPDATE, 1);
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WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
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WREG32_SOC15(MMHUB, 0, mmPCTL1_RENG_EXECUTE, pctl1_reng_execute);
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+ if (adev->powerplay.pp_funcs->set_mmhub_powergating_by_smu)
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+ amdgpu_dpm_set_mmhub_powergating_by_smu(adev);
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+
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} else {
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} else {
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pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
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pctl0_reng_execute = REG_SET_FIELD(pctl0_reng_execute,
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PCTL0_RENG_EXECUTE,
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PCTL0_RENG_EXECUTE,
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